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1. general description th e lpc15 x x ar e arm cor t ex-m3 b a sed m i cr ocon tr olle rs fo r em bed ded app lica t ions fe at ur ing a rich pe r i ph er al s e t with ve ry lo w p o w e r co nsu m pt ion . t h e ar m c o r te x -m 3 is a next generation core that of f e rs syst em enhancement s such as enhanced debug feat ures a nd a hig h e r level of su pp or t blo c k integ r a t io n. th e lpc15 x x ope ra te a t cpu fr equ encie s of up to 72 m h z. t he arm co rtex- m 3 cpu inc o r p o r ate s a 3- st a g e p i pe lin e an d us es a ha rva r d a r c h it ec tu re wit h s e p a r a t e loca l in stru ctio n and dat a b u ses as we ll a s a thir d bu s for p e r i phe ra ls. the arm cor t e x - m 3 cpu a l so in clu d e s an i n tern al pr efetch un it that su pp or t s specu l ative b r a n chin g. the lpc15xx includes up to 256 kb of fl ash memory , 32 kb of rom, a 4 kb eeprom, a nd up to 3 6 kb of sram. the p e r i ph era l co mplim ent includ es o ne full- spee d usb 2.0 d e vice , two spi inter f a c es, thr ee usar t s , on e fa st-m ode plu s i 2 c- bus inter f ace, o n e c_can module, pwm/timer s u bsy s tem with fo ur con f i gur ab le, m u lti-p u r pose s t ate configurable t i mers (sct imer/pw m ) with inpu t pr e- pr ocessing un it, a real- t ime clock module w i th indep endent pow e r supply and a dedicated osc illator , tw o 12-c hannel/12-bit, 2 m sa mple s/s adcs, on e 12- bit, 5 0 0 k samp les/s dac, fo ur vol t age com p a r a t o r s with in te rn al vo lt ag e refe ren c e, a nd a tem per atur e sensor . a dma eng ine can ser v ice most pe r i ph er als . fo r ad dition al docu m en t a tion r e lated to the l p c1 5xx p a r t s, see se ctio n 17 ? references ? . 2. features and benefit s ? system: ? arm co rtex- m 3 pr ocessor ( v ersio n r2 p1) , r u n n ing a t fre que ncies of up to 72 mhz. ? arm co rtex- m 3 bu ilt- i n nested v e ct or ed inter r u p t co ntro ller ( n vic). ? sys t em tick timer . ? ser i al wire de bug ( s wd) with four br eakpo int s and two watch p o i nt s. ? sing le- c ycle mu lt iplie r su pp or te d. ? me mor y pr otection unit (mpu) in clu ded . ? me mor y : ? up to 256 kb on -chip flash p r og ra mmin g mem o ry with 2 56 byte p a ge write an d er a s e. ? up to 36 kb sram. ? 4 kb eeprom. lpc15xx 32-bit arm cortex-m3 microcontrol ler; up to 256 kb flash and 36 kb sram; fs usb, ca n, rtc, spi, usart, i2c rev. 1 ? 19 february 2014 product data sheet http://
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 2 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller ? ro m api su pp or t: ? boo t lo ade r with boo t op tions fr om flash o r exter nal sou r ce via usar t , c_can, or usb ? usb drivers ? adc drivers ? spi drivers ? usar t drivers ? i2c driv ers ? powe r pr ofiles and p o wer m ode co nfigur at io n w i th lo w-p o w er m o de co n fig ur at ion op tio n ? dma driv ers ? c_can drivers ? fla s h in -app lication pro g r a mm ing ( i ap) a nd in- s ystem pro g r a mm ing ( i sp) . ? digit al peripherals : ? simp le dm a e ngin e with 1 8 chan nels an d 20 p r og ra mma ble inp u t tr igg e r s . ? high - spe ed gpio in te rface with up to 76 gene ra l-pur p o s e i/o ( g pio) pi ns with con f ig ur able p u ll- up /p ull- down r e sisto r s, o pen -d rai n mod e , in put inver t er , an d p r og ra mma ble dig i t a l glitch filte r . ? gp io interrupt generation c a p ability with boolean p a ttern-m atching feature on eight ex te rn al inp u t s. ? t w o gpio g r o upe d po rt inter r up t s . ? switch matrix for flexible config ur ation of ea ch i/o pin fun c tio n . ? crc en gin e . ? quad ra tu re en co der in te rface ( q ei). ? con f ig ur able pwm/timer / motor co ntro l sub s ystem: ? up to f o ur 32-bit counter/ timers or up to eig h t 1 6 - b it co unter /tim ers or com b ina t io ns o f 16 -b it an d 32 -bit timer s . ? up to 28 ma tch o u tput s an d 22 con f ig ur able ca ptur e inpu t s with inpu t mu ltiplexer . ? up to 28 pwm outp u t s tot a l. ? dither eng ine for im pr oved a v e r a ge r e solution of p u lse ed ges. ? fo ur s t a t e con f igur ab le t i me rs (sct imers) for highly fl e x ib le, ev en t- dr ive n tim i ng a nd pwm app lica t i ons. ? sct inp u t pr e- pro c esso r un it (sctipu) fo r p r o c e s sin g time r inpu t s an d im med i ate h and ling o f ab or t situ ation s . ? integ r a t e d with adc thr e sho l d co mp ar e inter r u p t s , temp er atur e se nsor , a nd an alo g comp a r ato r ou tp ut s for motor co ntro l fee d b a ck usin g ana log sign als. ? s p ec i a l-applic ation and s i mple timers: ? 2 4 -b it, four -cha nn el, m u lti-r a te timer ( m r t ) for re petitive inter r up t g ene ra tio n at up to four pro g r a mm able , fixed r a tes. ? rep e titive in te rr upt timer for gen er al pu rp ose use. ? wind owed w a tchd og timer (wwdt ) . ? high-resolution 32-bit real-time clock (rtc) with selectable 1 s or 1 ms time resolution running in the always-on power domain. rtc can be used for wake-up from all low power modes in cluding deep power-down.
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 3 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller ? ana l og p er i phe ra ls: ? t w o 12-bit adc with up to 12 input cha nne ls p e r adc a nd with multiple internal a nd exter nal trig ger inpu t s a nd samp le ra tes o f up to 2 m s a m ple s /s. each adc sup por t s two ind epe nde nt co nver sio n sequ ence s . adc co nver sion clock can b e the system clo c k or a n asyn chro no us clock der ived fro m one o f the thr e e pl ls. ? one 12 -b it dac. ? in te gr at ed t e m p er at ur e se nso r an d b a n d ga p in te rn al re fe re nc e v o lt a g e . ? f o u r co mp ar at or s w i th ex te rn al an d int e r n a l v o lt a g e r e fer e nce s (ac m p0 t o 3) . co m p ar a tor ou tp u t s ar e in te rn ally c o n n e c ted to th e sct i m e r /pwm s a n d adc s an d ex ternally to pins . each c o mp arator outp u t cont a i ns a pr ogr amm able glitch filter . ? ser i al inte rfaces: ? th re e usar t inter f aces with dma, rs-4 85 sup por t, au to ba ud, and with synchr ono us m ode and 3 2 khz mod e fo r wake- up fro m de ep -slee p and powe r- down mo de s. the usar t s sh ar e a fr action al bau d- ra te g ene ra to r . ? t w o spi co ntro llers. ? one i 2 c-bu s inter f a c e sup por ting fa st m ode an d f a st- m o de plu s with da t a r a tes o f up t o 1m b i t/s an d wit h mu ltip le ad d r e ss re co gn itio n an d m o n i to r m o de . ? one c_can controller. ? on e usb 2. 0 fu ll-sp e e d d e v i ce co nt ro ller wit h on -c hip ph y . ? clo ck ge ne r a t i o n : ? 12 mhz internal rc oscillator trimmed to 1 % acc u rac y for ? 25 ? c ? t amb ? +85 ? c tha t can o p tiona lly b e used a s a system clock. ? cryst al oscillator with an operat ing range of 1 m hz to 25 mhz . ? w a tchdog oscillator w i th a fr equency range of 503 k h z. ? 32 k h z low-power r t c osc illator with 32 kh z, 1 k h z, and 1 hz output s. ? syste m pl l allo ws cpu ope ra tio n up to the m a ximum cpu r a te with out the ne ed for a high-frequency cry s t a l. may be run fr om the sy stem oscillator or the internal rc os cillator . ? t w o a dditio nal pll s for g e n e ra ti ng the usb a nd sct i me r/pwm clo c ks. ? clock output function with divi der that c a n refl ec t the cryst al oscillator , the main clock, the irc , or the watchdog os cillator . ? powe r co ntro l: ? integ r a t e d pmu ( p ower m ana ge men t unit) to minim i ze p o wer co nsump t io n. ? red u ced p o wer mo de s: sleep m ode , dee p - s le ep mo de , power - d o wn mo de, and dee p powe r - down mo de . ? apis pr ovide d fo r op tim i zin g po we r consum ption in active and slee p mod e s and for con f ig ur ing dee p -sle ep, power - d o wn, a n d dee p powe r- down m ode s. ? w a ke -up fr om dee p -sle ep an d power - d o wn mod e s on activity on usb, usar t , spi, an d i2c p e r i phe ra ls. ? w a ke -up fr om slee p, de ep- sleep , power - down, an d de ep p o wer - do wn mod e s fro m th e r tc a l arm o r wake- up in te rr upt s. ? t i mer - con t r o lle d se lf wake- u p fr om deep power -d own mo de usin g th e r t c h i gh- re so lution /wake - up 1 khz time r . ? power-on reset (por). ? br ownou t detect bod) . ? jt ag b o u nda ry scan m ode s sup por ted. ? uniq ue de vice ser i al nu mbe r for id en tification.
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 4 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller ? sing le po we r supp ly 2 . 4 v to 3.6 v . ? t emp er atur e ra nge ? 40 c to +105 c. ? available as lqfp100, lqfp64, and lqfp48 packages. 3. applications 4. ordering information ? mo to r con t r ol ? solar inv e rters ? mo tio n drives ? home applianc es ? digit al power supplies ? build in g an d fa cto r y a u to m a t i on ? ind u str i al an d med i cal t a bl e 1. o r deri ng i n fo rma tio n type number package name description ve r s i o n l p c154 9jbd100 lqf p 1 0 0 p l a stic l o w profile q uad flat p a ckage ; 10 0 l ead s; bod y 14 ? 14 ? 1. 4 mm sot 4 0 7 - 1 l p c154 9jbd64 lqf p 6 4 pl astic l o w profile q uad flat p a ckage ; 64 le ads; b ody 10 ? 10 ? 1.4 mm sot3 14-2 l p c154 9jbd48 lqf p 4 8 pl astic l o w profile q uad flat p a ckage ; 48 le ads; b ody 7 ? 7 ? 1. 4 mm sot 3 1 3 - 2 l p c154 8jbd100 lqf p 1 0 0 p l a stic l o w profile q uad flat p a ckage ; 10 0 l ead s; bod y 14 ? 14 ? 1. 4 mm sot 4 0 7 - 1 l p c154 8jbd64 lqf p 6 4 pl astic l o w profile q uad flat p a ckage ; 64 le ads; b ody 10 ? 10 ? 1.4 mm sot3 14-2 l p c154 7jbd64 lqf p 6 4 pl astic l o w profile q uad flat p a ckage ; 64 le ads; b ody 10 ? 10 ? 1.4 mm sot3 14-2 l p c154 7jbd48 lqf p 4 8 pl astic l o w profile q uad flat p a ckage ; 48 le ads; b ody 7 ? 7 ? 1. 4 mm sot 3 1 3 - 2 l p c151 9jbd100 lqf p 1 0 0 p l a stic l o w profile q uad flat p a ckage ; 10 0 l ead s; bod y 14 ? 14 ? 1. 4 mm sot 4 0 7 - 1 l p c151 9jbd64 lqf p 6 4 pl astic l o w profile q uad flat p a ckage ; 64 le ads; b ody 10 ? 10 ? 1.4 mm sot3 14-2 l p c151 8jbd100 lqf p 1 0 0 p l a stic l o w profile q uad flat p a ckage ; 10 0 l ead s; bod y 14 ? 14 ? 1. 4 mm sot 4 0 7 - 1 l p c151 8jbd64 lqf p 6 4 pl astic l o w profile q uad flat p a ckage ; 64 le ads; b ody 10 ? 10 ? 1.4 mm sot3 14-2 l p c151 7jbd64 lqf p 6 4 pl astic l o w profile q uad flat p a ckage ; 64 le ads; b ody 10 ? 10 ? 1.4 mm sot3 14-2 l pc1517jbd48 lqfp48 plastic low profile quad flat package; 48 leads; body 7 ? 7 ? 1.4 mm sot313-2
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 5 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 4.1 o rdering options t abl e 2. o r de ri ng o p ti on s f or l p c15x x type number fl as h / kb eeprom / kb to t a l sram/ kb usb usart i 2 c spi c_can sctimer/ pwm 12-bit adc0/1 channels dac gpi o l p c154 9jbd100 25 6 4 36 yes 3 1 2 1 4 12 /1 2 1 76 l p c154 9jbd64 25 6 4 36 yes 3 1 2 1 4 12 /1 2 1 44 l p c154 9jbd48 25 6 4 36 yes 3 1 2 1 4 9/7 1 30 l p c154 8jbd100 12 8 4 20 yes 3 1 2 1 4 12 /1 2 1 76 l p c154 8jbd64 12 8 4 20 yes 3 1 2 1 4 12 /1 2 1 44 l p c154 7jbd64 64 4 1 2 y es 3 1 2 1 4 1 2 / 1 2 1 4 4 l p c154 7jbd48 64 4 1 2 y es 3 1 2 1 4 9 /7 1 3 0 l p c151 9jbd100 25 6 4 36 no 3 1 2 1 4 12 / 1 2 1 78 l p c151 9jbd64 25 6 4 36 no 3 1 2 1 4 12 / 1 2 1 46 l p c151 8jbd100 12 8 4 20 no 3 1 2 1 4 12 / 1 2 1 78 l p c151 8jbd64 12 8 4 20 no 3 1 2 1 4 12 / 1 2 1 46 l p c151 7jbd64 64 4 12 no 3 1 2 1 4 12 /1 2 1 46 l p c151 7jbd48 64 4 1 2 n o 3 1 2 1 4 9/7 1 32
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 6 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 5. marking th e lpc15 x x devices typica lly ha ve th e fo llowing top - side mar k in g for l q fp10 0 p a ckages: lp c15xx jxx x xxx xxx xx xxx yyw wxxx th e lpc15xx devices typically have the follo wi n g to p- sid e mar k ing for l q fp6 4 p a ckag es: lp c15 x x j xxx xxx xx xxx yyw wxxx th e lpc15xx devices typically have the follo wi n g to p- sid e mar k ing for l q fp4 8 p a ckag es: lp c15 x x j xxx xxx xxxyy wwx xx fie l d ?yy? st ates th e ye ar the device was m anu fa ctu r ed . fie l d ?ww? st ates th e week th e d e vice wa s ma nufactur ed d u rin g that ye ar . f i g 1 . l q f p 64/100 p ack age ma rking f ig 2. l q f p 48 p a cka ge mar king 1 n terminal 1 index area aaa-011231 aaa-011232 terminal 1 index area 1 n
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 7 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 6. block diagram grey-shaded b l ocks show per ip herals t hat ca n provid e hardw are tr igger s for dm a tr ansfers or have dma r equest lines. fi g 3. lpc1 5 x x bl oc k di ag ram arm cortex-m3 test/debug interf ace swd/etm systick nvic mpu processor core precision irc system pll watchdog oscillator usb pll sct pll frequency measurement system oscillator rtc oscillator clock generation sctipu 256/128/64 kb flash 32 kb rom 36/20/12 kb sram 4 kb eeprom 12-bit dac memory por t0/1/2 gint0/1 pint/ pattern match sctimer0/ pwm sctimer1/ pwm sctimer2/ pwm sctimer3/ pwm hs gpio qei dma trigger acmp0/ tempera ture sensor acmp1 acmp2 acmp3 input mux sctimer/pwm/mot or control subsystem spi0 usar t0 spi1 usar t1 fm+ i2c0 usar t2 c_can fs usb/ phy input mux syscon iocon pmu crc flash ctrl eeprom ctrl system/memory control mrt rit wwdt rtc timers serial peripherals 12-bit adc0 trigger mux analog peripherals 12-bit adc1 trigger mux ahb multilayer matrix ahb/apb bridges input mux input mux dma pads lpc15xx n pads n swm aaa-010869
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 8 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 7. pinning information 7.1 p inning fi g 4. lq fp4 8 p i n c onf igu r ati o n (w ith usb) lpc1547jbd48 lpc1549jbd48 37 pio0_22/i2c0_scl 24 pio0_16/adc1_9 38 pio0_23/i2c0_sda 23 pio0_15/adc1_8 39 v dd 22 pio0_14/adc1_7/ sct1_out5 40 v ss 21 pio0_13/adc1_6 41 v ss 20 v ss 42 v dd 19 pio0_12/dac_out 43 pio0_24/sct0_out6 18 pio0_11/adc1_3 44 pio0_25/acmp0_i4 17 v ssa 45 pio0_26/acmp0_i3/ sct3_out3 16 v dda 46 pio0_27/acmp_i1 15 pio0_10/adc1_2 47 pio0_28/acmp1_i3 14 vrefp_dac_vddcmp 48 pio0_29/acmp2_i3/ sct2_out4 13 pio0_18/ sct0_out5 1 pio0_0/adc0_10/ sct0_out3 36 usb_dm 2 pio0_1/adc0_7/ sct0_out4 35 usb_dp 3 pio0_2/adc0_6/ sct1_out3 34 reset/pio0_21 4 pio0_3/adc0_5/ sct1_out4 33 swdio/ pio0_20/sct1_out6/ tms 5 pio0_4/adc0_4 32 rtcxout 6 pio0_5/adc0_3 31 rtcxin 7 pio0_6/adc0_2/ sct2_out3 30 vbat 8 pio0_7/adc0_1 29 swclk/ pio0_19/tck 9 pio0_8/adc0_0/tdo 28 pio0_17/wakeup/trst 10 vrefp_adc 27 v dd 11 vrefn 26 xtalin 12 pio0_9/adc1_1/tdi 25 xtalout aaa-009352
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 9 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller fi g 5. lq fp4 8 p i n c onf igu r ati o n (w ith o u t usb) lpc1517jbd48 37 pio0_22/i2c0_scl 24 pio0_16/adc1_9 38 pio0_23/i2c0_sda 23 pio0_15/adc1_8 39 v dd 22 pio0_14/adc1_7/ sct1_out5 40 v ss 21 pio0_13/adc1_6 41 v ss 20 v ss 42 v dd 19 pio0_12/dac_out 43 pio0_24/sct0_out6 18 pio0_11/adc1_3 44 pio0_25/acmp0_i4 17 v ssa 45 pio0_26/acmp0_i3/ sct3_out3 16 v dda 46 pio0_27/acmp_i1 15 pio0_10/adc1_2 47 pio0_28/acmp1_i3 14 vrefp_dac_vddcmp 48 pio0_29/acmp2_i3/ sct2_out4 13 pio0_18/ sct0_out5 1 pio0_0/adc0_10/ sct0_out3 36 pio2_13 2 pio0_1/adc0_7/ sct0_out4 35 pio2_12 3 pio0_2/adc0_6/ sct1_out3 34 reset/pio0_21 4 pio0_3/adc0_5/ sct1_out4 33 swdio/ pio0_20/sct1_out6/ tms 5 pio0_4/adc0_4 32 rtcxout 6 pio0_5/adc0_3 31 rtcxin 7 pio0_6/adc0_2/ sct2_out3 30 vbat 8 pio0_7/adc0_1 29 swclk/ pio0_19/tck 9 pio0_8/adc0_0/tdo 28 pio0_17/wakeup/trst 10 vrefp_adc 27 v dd 11 vrefn 26 xtalin 12 pio0_9/adc1_1/tdi 25 xtalout aaa-009354
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 10 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller see t able 3 for the full pin name. fig 6. lqfp64 pin configuration (with usb) lpc1549jbd64 lpc1548jbd64 lpc1547jbd64 49 pio0_22 32 pio0_16 50 pio0_23 31 pio0_15 51 pio1_7 30 pio0_14 52 v dd 29 pio0_13 53 pio1_8 28 pio1_3 54 pio1_9 27 v ss 55 v ss 26 v ss 56 v ss 25 pio1_2 57 v dd 24 pio0_12 58 pio0_24 23 pio0_11 59 pio1_10 22 v dd 60 pio0_25 21 v ssa 61 pio0_26 20 v dda 62 pio0_27 19 pio0_10 63 pio0_28 18 vrefp_dac_vddcmp 64 pio0_29 17 pio0_18 1 pio0_30 48 usb_dm 2pio0_0 47 usb_dp 3 pio0_31 46 pio1_6 4pio1_0 45 reset/pio0_21 5pio0_1 44 swdio/ pio0_20 6pio0_2 43 rtcxout 7pio0_3 42 rtcxin 8pio0_4 41 vbat 9pio0_5 40 swclk/ pio0_19 10 pio0_6 39 pio0_17/wakeup 11 pio0_7 38 pio1_11 12 pio0_8 37 v dd 13 vrefp_adc 36 xtalin 14 vrefn 35 xtalout 15 pio1_1 34 pio1_5 16 pio0_9 33 pio1_4 aaa-009353
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 11 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller fi g 7. lq fp6 4 p i n c onf igu r ati o n (w ith o u t usb) lpc1519jbd64 lpc1518jbd64 LPC1517JBD64 49 pio0_22 32 pio0_16 50 pio0_23 31 pio0_15 51 pio1_7 30 pio0_14 52 v dd 29 pio0_13 53 pio1_8 28 pio1_3 54 pio1_9 27 v ss 55 v ss 26 v ss 56 v ss 25 pio1_2 57 v dd 24 pio0_12 58 pio0_24 23 pio0_11 59 pio1_10 22 v dd 60 pio0_25 21 v ssa 61 pio0_26 20 v dda 62 pio0_27 19 pio0_10 63 pio0_28 18 vrefp_dac_vddcmp 64 pio0_29 17 pio0_18 1 pio0_30 48 pio2_13 2pio0_0 47 pio2_12 3 pio0_31 46 pio1_6 4pio1_0 45 reset/pio0_21 5pio0_1 44 swdio/ pio0_20 6pio0_2 43 rtcxout 7pio0_3 42 rtcxin 8pio0_4 41 vbat 9pio0_5 40 swclk/ pio0_19 10 pio0_6 39 pio0_17/wakeup 11 pio0_7 38 pio1_11 12 pio0_8 37 v dd 13 vrefp_adc 36 xtalin 14 vrefn 35 xtalout 15 pio1_1 34 pio1_5 16 pio0_9 33 pio1_4 aaa-009376 fig 8. lqfp100 pin configuration lpc1548jbd100 lpc1518jbd100 76 100 50 26 1 25 75 51 aaa-009351
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 12 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 7.2 p in d escrip tion mo st pin s ar e config ura b le for multiple fu ncti on s, wh ich ca n be a n a lo g or digit a l. digit al in put s can b e con nected to seve ral p e r i phe ra ls a t o n ce, ho we ve r o n ly one dig i t a l ou tp ut or o ne an alo g fu nctio n can be assig ned to a n y o n pin . th e pin ? s conn ections to inter nal pe r i ph er al blo c k s a r e c o n fig ur ed b y the s witc h ma tr ix ( s wm ), th e in put multiplexer (input mux) , an d th e sct inp u t pre- pr ocessor unit (sctipu). the switch matrix enables certain fixed-pin functions that can only reside on specific pins (see table 3 ) and assigns all other pin functions (movable functions) to any available pin (see table 4 ), so th at the p i no ut can be op tim i ze d for a g i ve n ap plication . the input mux provides many choices (pins and internal signals) for selecting the inputs of the sctimer/pwms and the frequency measure block. pins that are connected to the input mux are listed in ta b l e 5 . if a pin is selec t ed in the inpu t mux, it is dire ctly con nected to the pe rip h e r al in put witho u t bein g ro uted thr o u gh the switch ma tr ix. ind epe nde ntly o f be in g s e le ct ed in th e in p u t m u x, th e sa me p i n ca n also b e assigne d by the switch ma trix to a nothe r pe rip her al inp u t. fo ur p i ns ca n also be con nected d i rectly to t he sctipu an d at the sa me time be in put s to the input mux and the switch matrix (see ta b l e 5 ). t able 3. pin de scr ip tio n wi th fixed-pin functions symbol lq fp48 lq fp64 lq fp10 0 res e t state [1] type de scr ip tio n pio0_0/adc0 _10/ sct0_out3 122 [2] i; pu io pio0 _0 ? gene ral purp o se port 0 i nput/outpu t 0. a ad c0_1 0 ? adc0 in put 10. o sct 0_out 3 ? sct i mer0/pwm output 3. pio0_1/adc0 _7/ sct0_out4 256 [2] i; pu io pio0 _1 ? gene ral purp o se port 0 i nput/outpu t 1. a ad c0_7 ? adc0 inp u t 7 . o sct 0_out 4 ? sct i mer0/pwm output 4. pio0_2/adc0 _6/ sct 1 _o ut3 368 [2] i; pu io pio0 _2 ? gene ral purp o se port 0 i nput/outpu t 2. ad c0_6 ? adc0 inp u t 6 . o sct 1_out 3 ? sct i mer1/pwm output 3. pio0_3/adc0 _5/ sct1_out4 471 0 [2] i; pu io pio0 _3 ? gene ral purp o se port 0 i nput/outpu t 3. a ad c0_5 ? adc0 inp u t 5 . o sct 1_out 4 ? sct i mer1/pwm output 4. pio0_4/adc0 _4 581 3 [2] i; pu io pio0 _4 ? gene ral purp o se port 0 i nput/outpu t 4. t h is is the isp_0 boo t pi n for the lqfp48 p a ckage. a ad c0_4 ? adc0 inp u t 4 . pio0_5/adc0 _3 691 4 [2] i; pu io pio0 _5 ? gene ral purp o se port 0 i nput/outpu t 5. a ad c0_3 ? adc0 inp u t 3 . pio0_6/adc0 _2/ sct2_out3 71 0 1 6 [2] i; pu io pio0 _6 ? gene ral purp o se port 0 i nput/outpu t 6. a ad c0_2 ? adc0 inp u t 2 . o sct 2_out 3 ? sct i mer2/pwm output 3. pio0_7/adc0 _1 81 1 1 7 [2] i; pu io pio0 _7 ? gene ral purp o se port 0 i nput/outpu t 7. a adc0_1 ? adc0 input 1.
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 13 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller pio0_8/adc0 _0/tdo 9 12 19 [2] i; pu io pio0 _8 ? gene ral purp o se port 0 i nput/outpu t 8. in boundary scan mode: tdo (test data out). a ad c0_0 ? adc0 inp u t 0 . pio0_9/adc1 _1/tdi 1 2 1 6 2 4 [2] i; pu io pio0 _9 ? gene ral purp o se port 0 i nput/outpu t 9. in boundary scan mode: tdi (test data in). a ad c1_1 ? adc1 inp u t 1 . pio0_10 /adc 1_2 15 19 28 [2] i; pu io pio0_10 ? general purpose port 0 input/output 10. a ad c1_2 ? adc1 inp u t 2 . pio0_1 1 / adc1 _3 18 23 33 [2] i; pu io pio0_11 ? general purpose port 0 input/output 11. on the lqfp64 package, this pin is assigned to can0_rd in isp c_can mode. a ad c1_3 ? adc1 inp u t 3 . pio0_12 /dac _ou t 19 24 35 [3] i; pu io pio0_12 ? general purpose port 0 i nput/output 12. if this pin is configured as a digital input, the input voltage level must not be higher than v dda . a da c_out ? dac an alo g output. pio0_13 /adc 1_6 21 29 43 [2] i; pu io pio0 _13 ? gen eral pu rpose po rt 0 inpu t/ou tp ut 13 . on th e lqf p 64 p a cka ge, thi s p in is assigne d to u0 _rxd in isp usar t mode. on the lqfp48 package, this pin is assigned to can0_rd in isp c_can mode. a ad c1_6 ? adc1 inp u t 6 . pio0_14 /adc 1_7/ sct1_out5 22 30 45 [2] i; pu io pio0 _14 ? gen eral pu rpose po rt 0 inpu t/ou tp ut 14 . on the lqfp48 package, this pin is assigned to u0_rxd in isp usart mode. a ad c1_7 ? adc1 inp u t 7 . o sct 1_out 5 ? sct i mer1/pwm output 5. pio0_15 /adc 1_8 23 31 47 [2] i; pu io pio0 _15 ? gen eral pu rpose po rt 0 inpu t/ou tp ut 15 . on the lqfp48 package, this pin is assigned to u0_txd in isp usart mode. a ad c1_8 ? adc1 inp u t 8 . pio0_16 /adc 1_9 24 32 49 [2] i; pu io pio0 _16 ? gen eral pu rpose po rt 0 inpu t/ou tp ut 16 . on the lqfp48 package, this is the isp_1 boot pin. a ad c1_9 ? adc1 inp u t 9 . pio0_17 /w akeup/ trst 28 39 61 [4] i; pu io pio0_17 ? general purpose port 0 input/output 17. in boundary scan mode: trst (t est reset). this pin triggers a wake-up from deep power-down mode. for wake up from deep power-down mode via an external pin, do not assign any movable function to this pin. pull this pin high externally while in deep power-down mode. pull this pin low to exit deep power-down mode. a low-going pulse as short as 50 ns wakes up the part. t able 3. pin de scr ip tio n wi th fixed-pin functions symbol lq fp48 lq fp64 lq fp10 0 res e t state [1] type description
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 14 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller pio0_18 / sct0_out5 13 17 26 [5] i; pu io pio0 _18 ? gen eral pu rpose po rt 0 inpu t/ou tp ut 18 . on th e lqf p 64 p a cka ge, thi s p in is assigne d to u0 _txd in isp usar t mode. on the lqfp48 package, this pin is assigned to can0_td in isp c_can mode. o sct 0_out 5 ? sct i mer0/pwm output 5. swclk/ pio0_19 /t ck 29 40 63 [5] i; pu i swclk ? se rial wi re clock. sw clk is e nab led by d e fault on th is pin. in boundary scan mode: tck (test clock). io pio0 _19 ? gen e ral pu rpose po rt 0 inpu t/ou tp ut 19 . swdio/ pio0_20 /sct 1_ out 6 / tms 33 44 69 [5] i; pu i/o swdio ? seria l wire deb ug i/o. swd i o i s en abl ed by d e fault on th is pin. in boundary scan mode: tms (test mode select). i/o pio0 _20 ? gen e ral pu rpose po rt 0 inpu t/ou tp ut 20 . o sct 1_out 6 ? sct i mer1/pwm output 6. res et /pio0_21 34 45 71 [6] i; pu i reset ? exte rn al reset inpu t: a low - goin g pulse a s sho r t as 50 ns on this pin rese t s th e device, causin g i/o p o rt s and p e riph erals to t a ke on the i r d e fault st ates, and p r o c essor execution to beg in at addre s s 0. in deep power-down mode, this pin must be pulled high externally. the reset pin can be left unconnected or be used as a gpio or for any mo vable function if an external reset function is not needed and the deep power-down mode is not used. i/o pio0 _21 ? gen e ral pu rpose po rt 0 inpu t/ou tp ut 21 . pio0_22 /i2c0 _ scl 37 49 78 [7] ia io pio0 _22 ? general purpose port 0 input/output 22. i/o i2c0 _scl ? i 2 c-bus clock input/out put. high - cu rre n t sink if i 2 c fa st-mode plu s i s sel e cte d in th e i/o con f ig uration register . pio0_23 /i2c0 _ sda 38 50 79 [7] ia io pio0 _23 ? general purpose port 0 input/output 23. i/o i2c0 _sda ? i 2 c - b u s da t a inp u t/ou tp ut. high-cu rre n t sink if i 2 c fa st-mode plu s i s sel e cte d in th e i/o con f ig uration register . pio0_24 /sct 0_ out 6 43 58 90 [8] i; pu io pio0 _24 ? general purpose port 0 input/output 24. high-current output driver. o sct 0_out 6 ? sct i mer0/pwm output 6. pio0_25 /acmp0_ i 4 44 60 93 [2] i; pu io pio0 _25 ? general purpose port 0 input/output 25. a ac mp0 _ i4 ? anal og comp arator 0 inp u t 4 . pio0_26 /acmp0_ i 3 / sct3_out3 45 61 95 [2] i; pu io pio0 _26 ? general purpose port 0 input/output 26. a ac mp0 _ i3 ? anal og comp arator 0 inp u t 3 . o sct 3_out 3 ? sct i mer3/pwm output 3. pio0_27 /acmp_i1 46 62 97 [2] i; pu io pio0 _27 ? general purpose port 0 input/output 27. a ac mp_ i 1 ? analo g co mp arator commo n inpu t 1. t able 3. pin de scr ip tio n wi th fixed-pin functions symbol lq fp48 lq fp64 lq fp10 0 reset state [1] type description
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 15 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller pio0_28 /acmp1_ i 3 47 63 98 [2] i; pu io pio0_28 ? general purpose port 0 input/output 28. a ac mp1 _ i3 ? anal og comp arator 1 inp u t 3 . pio0_29 /acmp2_ i 3 / sct2_out4 48 64 100 [2] i; pu io pio0_29 ? general purpose port 0 input/output 29. a ac mp2 _ i3 ? anal og comp arator 2 inp u t 3 . o sct 2_out 4 ? sct i mer2/pwm output 4. pio0_30 /adc 0_1 1 -1 1 [2] i; pu io pio0_30 ? general purpose port 0 input/output 30. a ad c0_1 1 ? adc0 inp u t 1 1 . pio0_31 /adc 0_9 -3 3 [2] i; pu io pio0_31 ? general purpose port 0 input/output 31. on the lqfp64 package, this pin is assigned to can0_td in isp c_can mode. a ad c0_9 ? adc0 inp u t 9 . pio1_0/adc0 _8 -4 5 [2] i; pu io pio1_0 ? general purpose port 1 input/output 0. a ad c0_8 ? adc0 inp u t 8 . pio1_1/adc1 _0 -1 5 2 3 [2] i; pu io pio1_1 ? general purpose port 1 input/output 1. a ad c1_0 ? adc1 inp u t 0 . pio1_2/adc1 _4 -2 5 3 6 [2] i; pu io pio1_2 ? general purpose port 1 input/output 2. a ad c1_4 ? adc1 inp u t 4 . pio1_3/adc1 _5 -2 8 4 1 [2] i; pu io pio1_3 ? general purpose port 1 input/output 3. a ad c1_5 ? adc1 inp u t 5 . pio1_4/adc1 _10 -3 3 5 1 [2] i; pu io pio1_4 ? general purpose port 1 input/output 4. a ad c1_1 0 ? adc1 in put 10. pio1_5/adc1 _1 1 -3 4 5 2 [2] i; pu io pio1_5 ? general purpose port 1 input/output 5. a ad c1_1 1 ? adc1 inp u t 1 1 . pio1_6/acmp_i2 -4 6 7 3 [2] i; pu io pio1_6 ? general purpose port 1 input/output 6. a ac mp_ i 2 ? analo g co mp arator commo n inpu t 2. pio1_7/acmp3_i4 -5 1 8 1 [2] i; pu io pio1_7 ? general purpose port 1 input/output 7. a ac mp3 _ i4 ? anal og comp arator 3 inp u t 4 . pio1_8/acmp3_i3/ sct3_out4 -5 3 8 4 [2] i; pu io pio1_8 ? general purpose port 1 input/output 8. a ac mp3 _ i3 ? anal og comp arator 3 inp u t 3 . o sct 3_out 4 ? sct i mer3/pwm output 4. pio1_9/acmp2_i4 -5 4 8 5 [2] i; pu io pio1 _9 ? gene ral purp o se port 1 i nput/outpu t 9. on the lqfp64 package, this is the isp_0 boot pin. a ac mp2 _ i4 ? anal og comp arator 2 inp u t 4 . pio1_10 /acmp1_ i 4 -5 9 9 1 [2] i; pu io pio1_10 ? general purpose port 1 input/output 10. a ac mp1 _ i4 ? anal og comp arator 1 inp u t 4 . pio1_1 1 - 3 8 5 8 [5] i; pu io pio1 _1 1 ? gene ral purp o se port 1 i nput/outpu t 1 1 . on the lqfp64 package, this is the isp_1 boot pin. pio1_12 - - 9 [5] i; pu io pio1_12 ? general purpose port 1 input/output 12. pio1_13 - - 1 1 [5] i; pu io pio1_13 ? general purpose port 1 input/output 13. t able 3. pin de scr ip tio n wi th fixed-pin functions symbol lq fp48 lq fp64 lq fp10 0 reset state [1] type description
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 16 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller pio1_14 /sct 0_ out 7 --1 2 [5] i; pu io pio1 _14 ? gen e ral pu rpose po rt 1 inpu t/ou tp ut 14 . o sct 0_out 7 ? sct i mer0/pwm output 7. pio1_15 - - 1 5 [5] i; pu io pio1 _15 ? gen e ral pu rpose po rt 1 inpu t/ou tp ut 15 . pio1_16 - - 1 8 [5] i; pu io pio1 _16 ? gen e ral pu rpose po rt 1 inpu t/ou tp ut 16 . pio1_17 /sct 1_ out 7 --2 0 [5] i; pu io pio1 _17 ? gen e ral pu rpose po rt 1 inpu t/ou tp ut 17 . o sct 1_out 7 ? sct i mer1/pwm output 7. pio1_18 - - 2 5 [5] i; pu io pio1 _18 ? gen e ral pu rpose po rt 1 inpu t/ou tp ut 18 . pio1_19 - - 2 9 [5] i; pu io pio1 _19 ? gen e ral pu rpose po rt 1 inpu t/ou tp ut 19 . pio1_20 /sct 2_ out 5 --3 4 [5] i; pu io pio1 _20 ? gen e ral pu rpose po rt 1 inpu t/ou tp ut 20 . o sct 2_out 5 ? sct i mer2/pwm output 5. pio1_21 - - 3 7 [5] i; pu io pio1 _21 ? gen e ral pu rpose po rt 1 inpu t/ou tp ut 21 . pio1_22 - - 3 8 [5] i; pu io pio1 _22 ? gen e ral pu rpose po rt 1 inpu t/ou tp ut 22 . pio1_23 - - 4 2 [5] i; pu io pio1 _23 ? gen e ral pu rpose po rt 1 inpu t/ou tp ut 23 . pio1_24 /sct 3_ out 5 --4 4 [5] i; pu io pio1 _24 ? gen e ral pu rpose po rt 1 inpu t/ou tp ut 24 . o sct 3_out 5 ? sct i mer3/pwm output 5. pio1_25 - - 4 6 [5] i; pu io pio1 _25 ? gen e ral pu rpose po rt 1 inpu t/ou tp ut 25 . pio1_26 - - 4 8 [5] i; pu io pio1 _26 ? gen e ral pu rpose po rt 1 inpu t/ou tp ut 26 . pio1_27 - - 5 0 [5] i; pu io pio1 _27 ? gen e ral pu rpose po rt 1 inpu t/ou tp ut 27 . pio1_28 - - 5 5 [5] i; pu io pio1 _28 ? gen e ral pu rpose po rt 1 inpu t/ou tp ut 28 . pio1_29 - - 5 6 [5] i; pu io pio1 _29 ? gen e ral pu rpose po rt 1 inpu t/ou tp ut 29 . pio1_30 - - 5 9 [5] i; pu io pio1 _30 ? gen e ral pu rpose po rt 1 inpu t/ou tp ut 30 . pio1_31 - - 6 0 [5] i; pu io pio1 _31 ? gen e ral pu rpose po rt 1 inpu t/ou tp ut 31 . pio2_0 - - 6 2 [5] i; pu io pio2 _0 ? gene ral purp o se port 2 i nput/outpu t 0. pio2_1 - - 6 4 [5] i; pu io pio2 _1 ? gene ral purp o se port 2 i nput/outpu t 1. pio2_2 - - 7 2 [5] i; pu io pio2 _2 ? gene ral purp o se port 2 i nput/outpu t 2. pio2_3 - - 7 6 [5] i; pu io pio2 _3 ? gene ral purp o se port 2 i nput/outpu t 3. pio2_4 - - 7 7 [5] i; pu io pio2 _4 ? gene ral purp o se port 2 i nput/outpu t 4. on th e lqf p 100 p a ckage , th is is the isp_1 boo t pi n. pio2_5 - - 8 0 [5] i; pu io pio2 _5 ? gene ral purp o se port 2 i nput/outpu t 5. on th e lqf p 100 p a ckage , th is is the isp_0 boo t pi n. pio2_6 - - 8 2 [5] i; pu io pio2 _6 ? gene ral purp o se port 2 i nput/outpu t 6. on the lqfp1 00 p a ckage , th is pi n is assign ed to u0_t xd in isp usar t mode. pio2_7 - - 8 6 [5] i; pu io pio2 _7 ? gene ral purp o se port 2 i nput/outpu t 7. on th e lqf p 100 p a ckage , th is pin is assign ed to u0 _rxd in isp usar t mode. pio2_8 - - 9 2 [5] i; pu io pio2 _8 ? gene ral purp o se port 2 i nput/outpu t 8. on th e lqf p 100 p a ckage , th is pin is assign ed to can0_td in isp c_can mode. t able 3. pin de scr ip tio n wi th fixed-pin functions symbol lq fp48 lq fp64 lq fp10 0 res e t state [1] type description
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 17 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller pio2_9 - - 9 4 [5] i; pu io pio2 _9 ? gene ral purp o se port 2 i nput/outpu t 9. on th e lqf p 100 p a ckage , th is pin is assign ed to can 0_rd in isp c_ can mo de. pio2_10 - - 9 6 [5] i; pu io pio2 _10 ? gen e ral pu rpose po rt 2 inpu t/ou tp ut 10 . pio2_1 1 - - 9 9 [5] i; pu io pio2 _1 1 ? gene ral purp o se port 2 i nput/outpu t 1 1 . pio2_12 35 47 74 [5] i; pu io pio2 _12 ? gen e ral pu rpose po rt 2 inpu t/ou tp ut 12 . on p a rt s lpc15 19/17/18 o n ly . pio2_13 36 48 75 [5] i; pu io pio2 _13 ? gen e ral pu rpose po rt 2 inpu t/ou tp ut 13 . on p a rt s lpc15 19/17/18 o n ly . u s b_ dp 35 47 74 [10 ] - i o u sb bid i rection a l d+ li ne. pa d includ es interna l 3 3 ? seri es termin a tion resistor . on p a rt s lpc1 549/48 /4 7 only . u s b_ dm 36 48 75 [10 ] - i o u sb b i di re cti o na l d ? lin e. pad i n clud es i n ternal 33 ? seri es termin a tion resistor . on p a rt s lpc1 549/48 /4 7 only . r t c x in 31 42 66 [9] - r tc oscil l ator inpu t. th is i nput shoul d be grou nded i f the r t c is not used. r t c x out 32 43 67 [9] - r tc oscil l ator output. xt alin 26 36 54 [9] - i np ut to th e oscilla to r circui t and i n ternal clo c k ge nerator circuit s . input volt age must not exceed 1.8 v . xt alout 25 35 53 [9] - o utput from the oscill ato r a m p lifier . vba t 30 41 65 - b attery su ppl y volt ag e. if no b a ttery is used, ti e vba t to vdd or to groun d. v dd a 16 20 30 - a na log sup p ly volt age . v dd and the an alo g re fe re nce vol t a ges vr efp_adc an d vrefp_dac_ vddcmp must n o t exce ed th e volt age l e vel on v dda . v dda shou ld typical l y be t h e sam e vo lt ag e s a s v dd b u t sho u ld be i solated to min imize no ise and error . v dda sh ould be tied to v dd i f the adc is no t used . v dd 39, 27, 42 22, 52, 37, 57 4, 32, 70, 83, 57, 89 - 3 .3 v supp ly volt age (2.4 v to 3.6 v). th e volt age l e vel on v dd must b e equal or l o wer than the an alog su pply vol t a ge v dda . vr efp_dac_ vddcmp 1 4 1 8 2 7 [9] - dac po sitive re fe rence volt ag e a nd an alog co mp a r ator refere nce volt age . th e vo lt age le ve l on vrefp_dac_ vd dcmp must b e equ al to o r lo wer th an the vol t ag e app lied to v dda . vr ef n 11 14 22 - a dc an d dac nega ti ve vo lt a ge reference . if th e adc is not used, tie vrefn to v ss . t able 3. pin de scr ip tio n wi th fixed-pin functions symbol lq fp48 lq fp64 lq fp10 0 res e t state [1] type description
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 18 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller [1] p in st ate at re set for default function: i = input; o = ou tput; pu = internal pull- up enabled; ia = inactive, no pull-up/dow n enabled; f = f l oating; if th e pins ar e not used, tie flo ating p i ns to gr ound or power to mi nimize po wer consumption. [2] 5 v tolera nt p ad pr oviding digit a l i/o functio ns w i th conf igurab le pull-up/pull-down resistor s, configurable hyste r esis, and an a l og input. when configured as ana log input, d i git al sect ion of the p ad is disa bled a nd the pin is not 5 v toler ant. t his pin includes a 10 ns on/of f glitch filte r . by def ault, th e glitch filter is turne d on. [3] this pin is not 5 v tolerant due to special analog functionalit y. when configured for a digita l function, this pin is 3 v to lerant and provid es st andar d digit al i/o functio ns w i th configurab le intern al pull- up and pull-do wn resistor s a nd hyster esis. wh en co nfigur ed for d ac_ o ut , the dig i t a l section of the pin is disabl ed and th is pin is a 3 v tolera nt analog outpu t. t his pin includes a 10 ns on/o f f glitc h filter . by default, the g l itch filter is turned o n. [4] 5 v tolera nt p ad pr oviding digit a l i/o functio ns w i th conf igurab le pull-up/pull-down resistor s, and configura ble hysteresis. t his pin includes a 10 ns on/o f f glitch filter . by d efault , th e g l itch filt er is turne d o n. t his pin is power ed in deep pow er-d own mode and can wake up th e p art. [5] 5 v tolera nt p ad pr oviding digit a l i/o functio ns w i th conf igurab le pull-up/pull-down resistor s and configura b le hysteresis. [6] 5 v tolerant pad. reset functionality is not avai lable i n d eep powe r-dow n mode. use the w akeup pin to reset t he ch i p and wake up fr om deep pow er- down mode. an e x ter nal pull-up resistor is required on this pin for the deep p ower- down mode . [7] i 2 c-bu s pins comp liant with the i 2 c-b us specification for i 2 c st andar d mode, i 2 c fa st- m ode, and i 2 c f ast- m ode plus. [8] 5 v tolera nt p ad pr oviding digit a l i/o functio ns w i th conf igurab le pull-up/pull-down resistor s and configura b le hysteresis; includes high-curr ent outpu t driver . [9] s pecial analog pin. [10] pad pr ovides usb functio ns. it is des igned in accordance with the usb specif ication, revision 2. 0 ( f ull- sp eed and low -speed mode only). th is p ad is not 5 v tolerant. vr ef p_adc 10 13 21 - a dc po sitive re fe rence volt ag e. the volt age l evel on vref p_adc must be e qual to or lowe r than the vol t a ge a ppli ed to v dd a . if the adc is not us ed, tie vrefp_adc to v dd . v ssa 17 21 31 - a na log g r o und . v ssa shoul d typi cally be the same volt ag e as v ss b u t sho u ld be isol ated to mini mi ze n o ise and e r ro r . v ssa shou ld be tied to v ss if the ad c i s no t use d . v ss 41, 20, 40 56, 26, 27, 55 88, 7, 39, 40, 68, 87 - g roun d. t able 3. pin de scr ip tio n wi th fixed-pin functions symbol lq fp48 lq fp64 lq fp10 0 res e t state [1] type description ta ble 4. mova ble fun c tion s fu nction name type desc rip t io n u0 _txd o t ra nsmitter ou tpu t for usar t0 . u0 _rxd i r eceive r in put for usar t 0 . u0 _r ts o request to send output for usart0. u0_cts i clear t o send i nput fo r usar t0. u0 _sclk i /o se rial clock inp u t/o u tput for usar t 0 in synchron ous mode. u1 _txd o t ra nsmitter ou tpu t for usar t1 . u1 _rxd i r eceive r in put for usar t 1 . u1 _r ts o request to send output for usart1.
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 19 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller u1_cts i clear t o send i nput fo r usar t1. u1 _sclk i /o se rial clock inp u t/o u tput for usar t 1 in synchron ous mode. u2 _txd o t ra nsmitter ou tpu t for usar t2 . u2 _rxd i r eceive r in put for usar t 2 . u2 _sclk i /o se rial clock inp u t/o u tput for usar t 1 in synchron ous mode. spi0_sck i/o s e r ial clock for spi0. spi0_mosi i /o ma ster ou t slave in for spi0. spi0_miso i /o ma ster in sl ave ou t for spi0. spi0_ssel0 i /o s l ave selec t 0 for spi0. spi0_ssel1 i /o s l ave selec t 1 for spi0. spi0_ssel2 i /o s l ave selec t 2 for spi0. spi0_ssel3 i /o s l ave selec t 3 for spi0. spi1_sck i/o s e r ial clock for spi1. spi1_mosi i /o ma ster ou t slave in for spi1. spi1_miso i /o ma ster in sl ave ou t for spi1. spi1_ssel0 i /o s l ave selec t 0 for spi1. spi1_ssel1 i /o s l ave selec t 1 for spi1. can0 _td o can0 tran smi t . can0 _rd i can0 receive. usb_vbus i usb vbus. sct 0_out 0 o sc t i mer0/pwm o u tput 0. sct 0_out 1 o sc t i mer0/pwm o u tput 1. sct 0_out 2 o sc t i mer0/pwm o u tput 2. sct 1_out 0 o sc t i mer1/pwm o u tput 0. sct 1_out 1 o sc t i mer1/pwm o u tput 1. sct 1_out 2 o sc t i mer1/pwm o u tput 2. sct 2_out 0 o sc t i mer2/pwm o u tput 0. sct 2_out 1 o sc t i mer2/pwm o u tput 1. sct 2_out 2 o sc t i mer2/pwm o u tput 2. sct 3_out 0 o sc t i mer3/pwm o u tput 0. sct 3_out 1 o sc t i mer3/pwm o u tput 1. sct 3_out 2 o sc t i mer3/pwm o u tput 2. sct_abor t 0 i s c t abor t 0. sct_abor t 1 i s c t abor t 1. adc0 _pintrig0 i a d c 0 exte rnal pi n trig ger inp u t 0. adc0 _pintrig1 i a d c 0 exte rnal pi n trig ger inp u t 1. adc1 _pintrig0 i a d c 1 exte rnal pi n trig ger inp u t 0. adc1 _pintrig1 i a d c 1 exte rnal pi n trig ger inp u t 1. dac_ pintrig i dac e x tern al pin trigg e r i npu t. dac_ shut of f i dac sh ut-o f f external i nput. acmp0_o o analog comparator 0 output. t a ble 4. mova ble fun c tion s ?continu ed function name type description
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 20 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller acmp1_ o o an alo g co mp arator 1 o u tput. acmp2_ o o an alo g co mp arator 2 o u tput. acmp3_ o o an alo g co mp arator 3 o u tput. cl kout o clock output. rosc o a n a lo g co mp arator ri ng oscill ator o u tput. rosc_reset i a nalog com p arator r i ng oscillator reset. usb_f t oggl e o usb frame to ggle . do no t assig n th is fun c tio n to a p in until a usb device i s con nected a nd the first sof in te rru p t h a s bee n receive d by the device. qei_ ph a i qei p hase a i npu t. qei_ ph b i qei p hase b i npu t. qei_ idx i qei i ndex inp u t. gpi o _int _bm a t o o u tput of the p a ttern match eng ine. swo o s e ri a l w i r e ou t p u t. t a ble 5. pin s co nn ecte d to the input mux and sc t ipu symbol lq fp48 lq fp64 lq fp10 0 des c ription pio0 _2/adc0_ 6/sc t 1_ out 3 3 6 8 s ct0 i npu t mux pio0 _3/adc0_ 5/sc t 1_ out 4 4 7 1 0 sct0 i npu t mux pio0 _4/adc0_ 4 5 8 1 3 sct2 i npu t mux pio0_5/adc0_3 6 9 14 fre q meas pio0 _7/adc0_ 1 8 1 1 1 7 s ct3 i npu t mux pio0 _14/adc1 _7/sct1 _out5 2 2 3 0 4 5 s ctipu inp u t sample_in_a0 pio0 _15/adc1 _8 23 31 4 7 sct1 i npu t mux pio0 _16/adc1 _9 24 32 4 9 sct1 i npu t mux pio0_17/wakeup/trst 28 39 6 1 sct0 i npu t mux sw clk/pio0_19 /t ck 29 40 6 3 fr eqmeas reset /pio0 _21 34 45 7 1 sct1 i npu t mux pio0 _25/acmp0_i4 4 4 6 0 9 3 s ctipu inp u t sample_in_a1 pio0 _27/acmp_i1 4 6 6 2 9 7 s ct2 i npu t mux pio0 _30/adc0 _1 1 - 1 1 f r e qmeas sct0 i npu t mux pio0 _31/adc0 _9 - 3 3 s ct1 i npu t mux pio1 _4/adc1_ 10 - 33 5 1 sct1 i npu t mux pio1 _5/adc1_ 1 1 - 34 5 2 sct1 i npu t mux pio1 _6/acmp_i2 - 46 7 3 sct0 i npu t mux pio1 _7/acmp3_i4 - 51 8 1 sct0 i npu t mux pio1 _1 1 - 38 5 8 sct3 i npu t mux sctipu input sample_in_a2 t a ble 4. mova ble fun c tion s ?continu ed function name type description
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 21 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 8. functional description 8.1 a rm cortex-m3 p r o cessor th e arm cor t ex-m 3 is a ge ne ra l p u r pose, 32 -bit micro p r o cessor , which of fer s hig h p e rfo rma nce an d ve ry low p o wer co nsump t io n. the arm corte x - m 3 of fer s ma ny new fea t u r e s , includ ing a th umb - 2 in str u ctio n set, low interrupt latency , h a r d war e division, hardware s i ngle-cy c le multi p ly , in te rr up tib l e/co ntinu abl e multiple lo ad a nd sto r e ins tr u ct ion s , au to m a t i c s t at e s a v e an d re sto r e f o r in te rr up t s , tig h t l y in te gr at ed in te rr up t con t r o lle r , and multiple cor e bu ses cap a b l e of sim u lt an eo us a c ce sses. pipe line techniq u e s are em ploye d so th at all p a rt s o f th e p r o c e s sing an d m e mo ry system s can op er ate con t in uo usly . t y pically , while on e in str u ctio n is b e in g e x e c u t e d , it s successo r is bein g de co ded , a nd a thir d instruction is be ing fetch e d fr om mem o r y . th e arm cor t ex-m 3 pr ocesso r is d e scrib ed in de t a il in the cortex-m3 t e chnical refer e n c e m anu al , wh ich is availa ble o n th e of ficia l arm website. 8.2 m emory protection unit (mpu) th e lpc15 x x have a m e mo ry pr otection unit ( m p u) wh ich ca n be u s e d to im pr ov e the reliability of an embedded sy stem by protecting critical dat a w i thin the user application. th e mpu a llows sep a r a ting pro c essin g t a sks by disallo win g access to ea ch other 's d a t a , d i sa bling access to memo ry r egio n s, allowing me mor y r e g i ons to b e de fined as re ad -on l y and de te ctin g une xpected me mor y a c cesses th at co uld po tentially br eak the system. th e mpu sep a rate s the me mor y in to d i stin ct r e g i o n s an d im ple m en t s pr ot ect i on b y p r eve n ting disallo we d acce sse s . t he mpu sup por t s up to eig h t r egio n s e a ch of which ca n be div i de d in to eig h t su br eg ion s . a cce sse s to m e mo ry locatio n s that a r e no t d e fine d in the mpu regions , or not permitted by the region s e tting, will c a use the memo ry management fa ult exce ption to t a ke p l ace. pio1 _12 - - 9 s ct0 inpu t mux pio1 _13 - - 1 1 sct0 i npu t mux pio1 _15 - - 1 2 sct1 i npu t mux pio1 _16 - - 1 8 sct1 i npu t mux pio1 _18 - - 2 5 sct2 i npu t mux pio1 _19 - - 2 9 sct2 i npu t mux pio1 _21 - - 3 7 sct3 i npu t mux pio1 _22 - - 3 8 sct3 i npu t mux pio1 _26 - - 4 8 sctipu inpu t sample_in_a3 pio1_27 - - 50 fre q meas t a ble 5. pin s co nn ecte d to the input mux and sc t ipu symbol lq fp48 lq fp64 lq fp10 0 description
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 22 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 8.3 o n - chip flash programming memory th e lpc15 x x co nt a i n up to 25 6 kb on -chip fla s h p r o g r a m mem o r y . th e fla s h ca n be p r og ra mme d using in- s ystem pr ogr amm i ng ( i sp) o r in- a p p lication pr og ra mming (iap) via th e o n - c h i p b o o t lo ad er so f tw a r e . f l as h up da te s via usb ar e su pp or te d as we ll. t h e fla s h m e mo r y is div i de d int o 4 kb s e ct or s with ea ch se ctor co nsistin g of 16 p age s. ind i vid ual p a g e s o f 2 56 byte ea ch ca n be er ased u s ing the iap e r a s e p a ge comm and . 8.3.1 isp pin c onfiguration th e lpc15xx sup por t s isp via th e usar t0, c_ can, or usb in te rfaces. th e isp mod e is de te rm in ed b y th e s t at e of two p i n s (isp_0 a nd isp_1) at b oot time: th e isp pin a s sig n me nt is dif f er ent fo r ea ch p a c k age, s o that the fewest f u nct ions po ss ible a r e b l oc ke d. no m o r e th an f o u r pin s m u st be s e t as ide f o r e n t e r i ng is p in a n y isp mod e . th e b oot cod e a s sign s two isp p i ns for each p a ckag e, which a r e pr ob ed wh en the p a r t b oot s to deter min e whethe r or n o t t o enter isp mode. on ce the isp mo de h a s b een d e ter m ine d , th e boo t lo ade r configu r e s the n e cessary ser i al pins fo r ea ch p a cka ge. pins which ar e n o t co nfigur ed b y the boo t lo ade r for th e selected b o o t mo de ( f or e x a m ple can0 _rd a n d can0_t d in usar t mo de ) can be a ssig ned to a n y fun ctio n th ro ugh th e switch matrix. 8.4 e eprom the lpc15xx cont ain 4 kb of on-chip by te-erasable and byte -programmable eeprom d a t a me mor y . th e eeprom can be pr og ra mmed u s in g in- a p p lication pr og ram m ing ( i ap) via the on -chip boo t loa d e r sof t wa re . t a ble 6. isp mo de s boot mode isp_0 isp_1 d escr ip tio n no isp h ig h h i g h i sp byp a ssed. part attempt s to boot from fla s h. if the use r cod e i n fl ash is n o t val i d, the n enters isp via usb. c_ can h igh l ow pa rt enters isp via c_can . usb l ow high par t enters isp via usb. usar t0 low l ow par t enters isp via usar t0. t a ble 7. pin assign me nt s for isp mo de s boot pin lqfp48 lqfp64 lq fp1 0 0 isp_0 p io0_4 pio1_9 pio2_5 isp_1 p io0_16 pio1 _1 1 p io2_ 4 usar t mode u0 _txd pio0_15 pio0 _18 pio2_ 6 u0 _rxd pio0_14 pio0 _13 pio2_ 7 c_ can mode can0 _t d p io0_18 pio0 _31 pio2_ 8 can0 _rd p io0_13 pio0 _1 1 p io2_ 9 usb mode usb_vbus (same as isp_1 ) pio0_16 pio1 _1 1 pio2_4
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 23 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 8.5 s ram th e lpc15 x x co nt a i n a to t a l 36 kb, 2 0 kb or 12 kb o f con t ig uou s, on -chip st a t ic ram me mor y . for e a ch sram con f igur a t io n, t h e sram is div i de d in to th re e b l ocks: 2 x 16 kb + 4 kb f o r 3 6 kb s r am , 2 x 8 kb + 4 kb fo r 2 0 kb sram , an d 2 x 4 k b + 4 k b fo r 12 k b sram. th e bo ttom 1 6 kb, 8 kb, or 4 kb ar e en able d by th e boo tload er a nd can not be dis a bled. the nex t t w o sram blocks in each configurat ion can be disabled or enabled individually in the syscon block to save power . 8.6 o n - chip rom th e on -chip rom con t ain s the b oot load er an d th e fo llo win g ap plic atio n pr og ra m m in g interfaces (api s): ? in -sy s te m pr o g r a m m i ng (is p ) an d i n - a pp lica tio n pr og ra m m i ng (iap ) su pp or t fo r fla s h in clu d ing iap er ase p a ge com m an d. ? iap support for eep rom. ? fla s h upd ates via usb and c_can su ppo rted . ? usb api (hid, c dc, and msc drivers). ? dma, i2c, usar t , spi , and c_ can dr ive r s. ? powe r pr ofiles fo r configu r in g po we r consum ption a nd pll setting s. ? powe r mod e configu r a t io n for con f ig ur ing de ep -slee p , p o wer - d o wn, and d eep power-down modes. ? adc d r iver s for a n a l og- to-d igit a l con v ersio n and adc calibr a tion. t a ble 8. lpc1 5xx sram co nfigu r ation s sram0 sram1 sram 2 l p c154 9/19 (tot a l sra m = 36 k b ) ad dress range 0x02 00 000 0 to 0x02 00 3f ff 0x0 200 40 00 to 0x0 200 7f f f 0 x 020 0 8 000 to 0 x 020 0 8 ff f size 16 kb 16 kb 4 kb con t rol c ann ot b e d isabl ed di sable / e nab le d isab le/ena ble de fa ult ena ble d en abl ed e nab led l p c154 8/18 (tot a l sra m = 20 k b ) ad dress range 0x02 00 000 0 to 0x02 00 1f ff 0x0 200 20 00 to 0x0 200 3f f f 0 x 020 0 4 000 to 0 x 020 0 4 ff f size 8 kb 8 kb 4 kb con t rol c ann ot b e d isabl ed di sable / e nab le d isab le/ena ble de fa ult ena ble d en abl ed e nab led l p c154 7/17 (tot a l sra m = 12 k b ) ad dress range 0x02 00 000 0 to 0x02 00 0f ff 0x0 200 10 00 to 0x0 200 1f f f 0 x 020 0 2 000 to 0 x 020 0 2 ff f size 4 kb 4 kb 4 kb con t rol c ann ot b e d isabl ed di sable / e nab le d isab le/ena ble default enabled enabled enabled
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 24 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 8.7 a hb multilayer matrix fig 9 . ahb multilaye r matrix arm cortex-m3 test/debug interface dma ahb-t o-apb bridge0 ahb-to-apb bridge1 eeprom hs gpio slaves sram2 system bus i-code bus d-code bus masters flash rom ahb mul tila yer ma trix = master-slave connection dac acmp wwdt adc0 rit i2c0 qei swm spi0 spi1 usart1 pmu syscon usart2 pint gint0 gint1 mr t adc1 usb sram0 sram1 sctimer0/pwm sctimer1/pwm sctimer2/pwm sctimer3/pwm crc input mux rtc sctipu flash ctrl iocon eeprom ctrl usart2 c_can aaa-010870
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 25 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 8.8 m emory map see section 8.5 ? sram ? for sram configuration. fig 10. memory map 0x4000 4000 0x4000 8000 0x4000 c000 0x4001 8000 0x4002 8000 0x4003 8000 0x4003 c000 0x4004 0000 0x4004 4000 0x4004 8000 0x4004 c000 0x4005 0000 0x4005 8000 0x4005 c000 0x4008 0000 0x4008 0000 0x4001 c000 0x4001 4000 0x4000 0000 0x4002 c000 0x4003 0000 reserved 256 kb flash 0x0000 0000 0 gb 4 gb 0x0200 0000 0x0300 8000 0x0320 0000 0x0320 1000 0x1c01 0000 0x1c01 4000 0xffff ffff 4 kb eeprom reserved reserved 0x1000 0000 0x1c00 0000 apb peripherals 0 0x1c01 8000 0x1c01 c000 0x1c00 4000 crc gpio 0x1c00 8000 0x1c00 c000 dma 0x1c02 4000 0x4000 0000 0x4008 0000 apb peripherals 1 0x400f 0000 0x0200 9000 36 kb sram (lpc1549/19) 0x0200 5000 20 kb sram (lpc1548/18) 0x0200 3000 12 kb sram (lpc1547/17) reserved lpc15xx 0x0004 0000 32 kb boot rom 0x0000 0000 0x0000 00c0 active interrupt vectors reserved 0x0300 0000 reserved reserved reserved reserved reserved sct imer0/pwm 0x1c02 0000 sctimer1/pwm sct imer2/pwm 0x1c02 8000 sctimer3/pwm 0x4005 4000 0x4007 4000 0xe000 0000 0xe010 0000 private peripheral bus 0x4007 8000 adc0 dac analog comparators acmp reserved reserved rt c wwdt reserved usar t0 qei reserved usar t1 spi0 reserved i2c0 syscon input mux reserved switch matrix swm pmu spi1 reserved 0 1 2 4:3 5 6 9:7 16 15 14 17 18 19 22 20 21 28:23 29 10 11 13:12 31:30 apb peripherals 0x4008 4000 0x400a 0000 0x400a 4000 0x400a c000 0x400b 4000 0x400c 0000 0x400c 4000 0x400e 8000 0x400e c000 0x400f 0000 0x400f 4000 0x400f 8000 0x400f 0000 0x400b 0000 0x400a 8000 0x400b 8000 0x400b c000 0x400f c000 adc1 reserved mr t reserved rit sctipu flash ctrl fmc reserved pint reserved c_can iocon gint0 gint1 usar t2 reserved reserved eeprom ctrl 0 7:1 8 9 10 11 12 26 25:17 16 27 28 29 30 31 13 14 15 usb aaa-010871
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 26 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 8.9 n ested v e ctored in terrupt con t roller (nvic) th e neste d v e ctor ed inter r u p t con t r o lle r ( n vi c) is p a rt of the cortex-m3. the tight coupling to the cp u allows for lo w in terr up t la te ncy a n d e f ficien t p r oce s sing of la te ar riving in te rr upt s. 8.9 .1 fea tures ? nested v e ctor ed inter r u p t co ntro ller tha t is an inte gra l p a rt of the arm cor t e x - m 3 . ? t i ghtly coupled interrupt controll er provides low interrupt latenc y . ? con t r o ls syste m exception s a nd pe rip her al inte rr upt s. ? th e nvic su ppo rt s 47 vector ed inter r upt s. ? eigh t p r og ra mma ble inte rr upt pr ior i ty leve ls w ith hardware pr iority level masking. ? so f twa re in te rr up t ge ne ra tio n u sing t h e ar m ex cep tio n s svc all an d pe nd sv . ? su pp or t for n m i . ? arm co rtex- m 3 v e ctor t a ble o f fs et r e g i ste r vt or imple m en te d. 8.9 .2 inte r rupt s ources t y p i ca lly , e a ch per iph e r a l de vice ha s o ne inte rr upt line con nected to the nvic bu t can h a ve se ve ra l i n terr up t flag s. in dividu al inter r u p t fla g s can a l so re pre s ent mor e than o n e in te rr upt sour ce. 8.10 iocon blo ck th e iocon b l ock con f igur es th e ele c trica l p r o per ties o f the p i ns such a s pu ll-u p an d pull-down resis t ors, h ystere s is, ope n- dr ain mo des an d inpu t filter s. remark: t he pin fu nctio n an d wh ethe r th e pin o p e r ate s in dig i t a l or ana log mo de a r e e n tire ly un der th e contr o l of the switch m a trix. ena b lin g an a nalo g fu nction thr oug h the switch ma tr ix d i sa bles the dig i t a l p ad. ho wever , the in tern al pu ll-u p an d pu ll-d o wn r e sisto r s as we ll as th e pin h y ster esis must b e disa bled to ob t a in a n accu ra te r e a d in g of the ana log in put. 8.10 .1 fea tures ? pr ogr amm able pull- up , pu ll-d o wn, or r epe ater mod e . ? all pin s (e xce p t pio0 _2 2 and pio0 _2 3) a r e p u lled u p to 3.3 v ( v dd = 3.3 v) if their p u ll-u p re sistor is en abled. ? pr ogr amm able p s eu do o pen -d ra in mod e . ? pr ogr amm able (on / of f) 10 ns glitch filter on 36 pins (pio0 _0 to pio0_ 17, pio0_2 5 to pio0_ 3 1 , pio1_ 0 to pio1_1 0) . th e glit ch filter is tur ned o n by defau lt. ? pr ogr amm able hyster esis. ? pr ogr amm able inpu t inve rter . ? digit al filter with pr og ram m ab le filte r const a n t o n all pin s . 8.10 .2 s t an dard i/o p ad c onfiguration fig u r e 1 1 shows the possible pin modes for standard i/o pins with analog input function:
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 27 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller ? digit al output driver with c o n fig ur ab le o p e n - d ra in ou tp ut ? digit a l in pu t: w e ak pull- up r e sisto r (pm o s device) e n a b led / d i sa ble d ? digit a l in pu t: w e ak pull- do wn r e sisto r ( n m o s device) e nab led / d i sa ble d ? digit a l in pu t: re pea ter mo de e nab led / d i sa bled ? digit al input: input digit a l f ilter c o nfigurable on all pins ? digit a l in pu t: in put glitch filte r en able d /disab led on se lect pi ns ? ana l og in put 8.1 1 switch matrix (swm) th e switch matr ix contr o ls th e fu nctio n of each d i git a l o r mixed a nalo g /dig it al pin in a highly flexible way by allowin g to con nect m any fu nctions like th e usar t , spi, sct , and i2c fu ncti ons to a n y pin tha t is n o t p o wer or g r ou nd . th ese fu nctions ar e ca lled m o vable fun c tion s a nd ar e liste d in t able 4 . functions that need specialized pads like th e adc or analog comparator inputs can be enabled or disabled through the switch matrix. these functions are called fixed-pin functions and cannot move to other pins. the fixed-pin functions are listed in ta b l e 3 . if a fixed-pin function is disabled, any other mov able function can be assigned to this pin. fi g 1 1 . s t a nda rd i/o p in c on f ig urat ion pin v dd v dd esd v ss esd strong pull-up strong pull-down v dd weak pull-up weak pull-down open-drain enable output enable repeater mode enable pull-up enable pull-down enable select data inverter data output data input select glitch filter analog input select analog input pin configured as digital output driver pin configured as digital input pin configured as analog input programmable digital filter 10 ns glitch filter aaa-010776
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 28 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 8.12 fast general-purpo se p a rallel i/o (gpio) device pin s that ar e no t conn ected to a specific pe rip h e r al func tion t h rough the switc h ma tr ix ar e co ntro lled by th e gp io r egister s. pin s ma y be dy na mically con f ig ur ed as in put s o r ou tp ut s. mu ltip le ou tp ut s ca n be set or clea re d in on e wr ite ope ra tio n . l p c1 5xx use a c cele ra te d gpio function s. ? an en tire p o rt value can be written in o ne instru ctio n. ? ma sk, se t, and cle a r o per ation s a r e sup por ted for the e n tire por t. 8.12 .1 fea tures ? bit le vel por t r e g i ster s a llow a sin g le in str u ctio n to se t an d clear any num ber of b i t s in o ne write op er ation . ? direction c o ntrol of individual bit s . 8.13 pin interrupt/p a ttern match engine (pint) th e pin inter r up t b l ock con f igur es up to e i ght pin s fro m th e dig i t a l pin s o n po rt s 1 an d 2 for p r ovid ing eig h t exte rn al inter r u p t s co nne cted t o th e nvic . t h e in p u t m u x b l ock is us ed to sele ct th e pin s . th e p a tte r n m a tch e n g i ne can b e used, in conju n ction with so f t war e , to cr eate com p lex st ate ma ch ine s ba se d on p i n inp u t s . any digit a l pin on port s 0 and 1 can be configured through the syscon block as input to th e pin in te rr up t or p a tte r n ma tc h e n g in e . t h e r e gist er s t h a t co ntr o l th e pin in te rr up t or p a tter n match eng ine a r e lo ca te d on the io + bu s f o r f a st si n g l e - c yc l e a cc e s s . 8.13 .1 fea tures ? pin in te rr upt s ? up to eig h t pins ca n be sele cte d fr om a ll d i git a l p i ns o n po rt s 0 and 1 as e dge - or le vel-se nsitive in te rr upt re qu est s . each re que st cre a tes a se p a ra te in te rr up t in the nvic . ? edge-sensitive interrupt pins c a n interrup t on rising or falling edges or both. ? l e vel- sensitive inter r up t p i ns can be high- or l o w - a c tive. ? pin in terr up t s can wake u p th e p a rt fr om slee p mod e , dee p- sle e p mo de , an d po we r- do wn m o d e . ? pin int e r r u p t p a tt er n m a tc h en g i ne ? up to 8 pin s can b e se lected fro m all digi t a l pins on p ort s 0 an d 1 to co ntrib ute to a b o o l ean e x pre s sio n . t he bo ole an exp r ession con s ist s of sp ecifie d levels and /or tr ansition s on va rio u s com b ina t io ns of the s e pins. ? eac h m i n te r m ( p r o du ct te rm ) co mp ris i ng th e sp e c ifie d bo o l ea n ex pr es sion c a n g e n e r a te it s own , de dicated in te rr up t r equ est. ? any occurrence of a p a ttern match can be programmed to also generate an rxev notific a t ion to t h e ar m cpu. ? the pattern match engine d oes not facilitate wake-up.
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 29 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 8.14 gpio group interrupt s (gint0/1) th e gpio pin s can b e used in sever a l ways to set pins as inpu t s or outp u t s a nd u s e the in put s as comb ina t io ns of level a n d edg e sen s itive inter r upt s. for ea ch por t/p i n con nected to on e of th e two the gpio gro upe d inter r upt block s (gi nt0 and gi nt1), t h e g p io gr o u p e d in te rr up t re gis te r s de te rm in e whic h pin s ar e en ab le d to ge n e r a t e int e r r u p t s a n d wha t the a c tive pol aritie s of each o f those in put s ar e. the gpio grouped in terrupt registers also se lect whether the interrup t output w ill be level or edge triggered and whether it will be based on the or or th e and of all of the enabled in put s. whe n th e de sig nate d p a tter n is detected o n the se lected in put pins, th e gpio gr oup ed interrupt blo c k gen erates an inte rrupt. if the p a rt is in a p o wer - saving s mo de, it fir s t a s ynchr o n ously wa ke s the p a r t u p pr ior to asser t in g the inte rr upt re que st. the in te rr up t r equ est lin e ca n be clea re d by wr iting a o ne to th e inter r u p t st a t u s b i t in the con t r o l r egister . 8.14 .1 fea tures ? t w o gr ou p inter r u p t s a r e su ppo rted to r e flect two distin ct inter r u p t p a tter ns. ? th e inp u t s fro m an y n u mb er of digit a l pin s can be e n a b led to co ntrib u te to a co mbin ed g r ou p inter r u p t. ? the p o la rity o f each inpu t enab led for th e gro u p in te rr up t can b e co nfigu r ed high or lo w . ? enab led in te rr up t s can b e logica lly comb ined th ro ugh a n or or and o per ation . ? th e gr oup ed in te rr up t s can wake up th e p a rt fr om slee p, d e e p -sle ep or powe r - down mo de s. 8.15 dma controller th e dma con t rolle r can a c cess all memo ri e s a nd the usar t , spi, i2c, and dac pe r i ph er als u s in g dm a re q u e s t s . dm a tra n s fe rs ca n als o be tr igg e r e d by in ter n al e v e n t s like the adc in te rr upt s, th e sct dma re que st signa ls, or th e ana log com p a r a t o r outp ut s. 8.15 .1 fea tures ? 1 8 ch ann els with 1 4 ch ann els co nne cte d to p e r i ph era l req u e s t inpu t s. ? dma ope ra tio n s ca n be trig ge red by o n - c h i p even t s . each dma cha n n e l ca n select o ne trig ger inpu t fro m 24 sou r ces th ro ugh the inpu t mu x. ? pr iori ty is user select ab le fo r ea ch ch ann el. ? continuous priority arbi tration. ? ad dr es s ca ch e wit h f o u r en tr ies . ? ef f i cien t us e of da t a b u s. ? su pp or t s sing le tr an sf er s u p to 1 ,0 2 4 wo rd s. ? add r e s s incre m en t o p tions allo w p a cking an d/or u n p a cking d a t a .
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 30 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 8.16 input multiplexing (input mux) the input mux allows to selec t fr om mu lti p le exter nal a nd inter n a l so urce s for the sct in put s, dma trig ger inpu t s , an d th e fr eq ue ncy me asur e blo c k. t he inp u t mux is imp l eme n ted as a re gister inter f a c e with o n e so ur ce se lectio n r egister fo r e a ch in put. the in put mux ca n for e x a m ple con n e c t sct o u tput s, th e adc inter r u p t s , or th e comp ar ator o u tput s to th e sct in put s an d th us e n a b les th e sct to u s e a la rg e varie t y of even t s to co nt ro l th e tim i n g op er at ion . th e adcs a nd a n a l og co mp ara t o r s a l so su pp ort in put mu ltip lexing using so ur ce selection r egister s a s p a r t of th eir con f igur ation r e g i ster s. 8.17 usb interface remark: t he usb in te rface is a v ailab l e on p a r t s l p c1 549 /48/47 o n ly . the univers a l serial bu s (usb) is a 4- wir e bu s tha t supp or t s comm unica tio n betwee n a h o st an d on e or mo re ( u p to 1 27) per iph e r a ls. th e host co ntro ller a llocates th e usb b and wid t h to att a che d devices th ro ugh a to ke n- based pro t o c ol. t he bu s sup por t s h o t-p l ugg ing an d d y n a mic co nfigur ation o f th e d e vices. all transact i ons are initiated by the host controller . th e usb inter f ace consist s o f a full- sp ee d device contr o ller with on -chip phy (physica l la ye r) for device function s. remark: configure the part in default power mode with the power profiles before using the usb (see section 8.40.1 ) . do no t use the usb wh en the p a r t r u n s in pe rfor ma nce, e f ficiency , or lo w- po we r mo de. 8.17 .1 full - speed usb dev ice con trol ler th e de vice con t r o lle r en able s 12 mbit/s da t a exchan ge with a usb host con t r o lle r . it con s ist s o f a r e g i ster inter f a c e , ser i al inter f ace eng ine , an d en d p oint bu f f er memo ry . the ser i al inter f ace eng ine d e cod e s the usb dat a stre am a nd writes dat a to the a p p r o p ria t e e n d poin t bu f f er . th e st a t u s of a comp leted usb tran sfe r o r er ro r co ndition is in dicated via st atus re giste r s. an in te rr up t is a l so gen er ated if ena ble d . 8.17 .1 .1 fe at ures ? de dic a t e d us b pl l ava ila ble . ? fully compliant with usb 2.0 specification ( f u ll spe e d ) . ? sup p o r t s 1 0 ph ysical (5 logical) end p o int s includ ing on e contr o l end p o int. ? sing le an d dou ble b u f f e r in g supp or te d. ? each n on- contr o l end po int su ppo rt s bu lk, inter r u p t, or iso c h r o n o u s e n d p o i nt types. ? sup p o r t s wa ke -u p fr om dee p - s le ep mo de a nd power - d o wn mo de o n usb activity a nd re mote wake- u p . ? sup p o r t s so f t co nne ct functiona lity thr oug h inter n a l p u ll- up r e sistor . ? internal 33 ? se ries term ina t io n re sistor s on usb_dp and usb_dm lines eliminate the n eed fo r extern al ser i es r e sisto r s. ? supports link power management (lpm).
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 31 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 8.18 usart0/1/2 remark: all usar t fun c tion s a r e mo va ble fun c tio n s a nd a r e a s sign ed to pin s thr oug h th e swit ch m a tr ix. do n o t co nn e c t usar t f u n c t i on s t o th e op en -d r a in p i ns pio 0 _2 2 an d pio0 _23 . inter r u p t s gen er ated by the usar t p e rip h e r a l s can wake up th e p a rt fr om dee p - s le ep a nd po we r- do wn m ode s if th e usar t is in synchr o n ous mod e , th e 32 khz mo de is e nab led, or th e ct s inte rr upt is e nab led. 8.18 .1 fea tures ? ma xim u m bit ra te s o f 4.5 mb it/s in asyn ch ro no us m ode , 15 mbit/s in syn c hro n o u s m o d e m a st er m o de , a n d 18 m b it/s in syn ch ro no u s s l ave m o de . ? 7 , 8, or 9 d a t a b i t s an d 1 or 2 stop b i t s . ? synchr ono us mo de with ma ster or sla v e op er ation. includ es dat a pha se selection a n d cont inuous clock option. ? mu ltip ro ce sso r /mul tid r o p (9- b it) m ode with sof t wa re a d d r ess co mp ar e. ? rs-4 85 tra n sceiver o u tput en able . ? autob a u d mod e fo r au to matic bau d ra te d e tection ? par i ty ge ne ratio n and ch eckin g : odd , eve n , o r no ne. ? sof t war e select ab le over samp ling fro m 5 to 1 6 clocks in asynchr ono us mod e . ? one tra n smit a nd o ne r e ceive da t a buf fer . ? r ts/ct s fo r har dwar e sig nalin g for a u toma tic flow con t r o l. so f t war e flo w co ntro l can b e per form ed u s in g de lt a cts d e tect, t r an sm it disable con t rol, an d any gpio as an r t s outpu t. ? received dat a a n d st atus ca n op tio n a lly be r e a d fr om a sin g le r egister ? br eak gen er ation a nd d e tectio n. ? re ce ive da t a is 2 of 3 sa mp le "vo tin g" . s t a tu s f l ag s e t wh en o n e s a m p le dif fer s. ? built- i n baud ra te gen e ra to r with auto- ba ud fun c tion . ? a fr actiona l rate d i vid e r is sh ar ed a m on g all usar t s . ? inter r u p t s availab l e for receiver re ad y , t r an sm itter re ady , receiver idle , cha nge in r e ceiver b r e a k detect, fr am ing er ro r , par i ty er ro r , over ru n, und e r r u n , de lt a ct s detect , and receiv er sa mple noise detect ed. ? l oop back mod e fo r testin g of dat a a n d flow co ntro l. ? in syn c h r o nou s slave mo de , wakes u p the p a r t fro m dee p- sle e p a nd po wer- do wn mo de s. ? s p e c i a l ope ra tin g mod e allo ws op era t ion at up to 96 00 b aud u s ing the 32 khz r t c os cillator as the u a r t clock . this mode can be used while the device is in dee p - s le ep or power - d o wn mod e an d ca n wa ke-u p the de vice whe n a char acter is received. ? usar t tra n smit a nd r e ceive function s work with the s yst em d m a co nt ro ller . 8.19 spi0/1 all spi function s ar e mo va ble fun c tion s a nd ar e assign ed to pin s thr oug h th e switch matrix. do not connect spi functions to the open-drain pins pio0_22 and pio0_23.
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 32 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 8.19 .1 fea tures ? ma xim u m da t a ra te s o f 17 m b it/s in ma st er mod e and sla v e m ode fo r spi function s co nn e c te d to a ll d i git a l p i ns ex ce pt pio 0 _2 2 an d pio 0 _2 3. ? dat a tra n smit s of 1 to 16 b i t s sup por ted dir e ctly . la rg er fr ame s supp or te d by so f t war e . ? m as t er a nd s l av e op er at ion . ? dat a can b e tra n smitte d to a sla v e witho ut the nee d to rea d incom i ng da t a . this ca n b e useful while setting up a n spi me mor y . ? control information c a n optionall y be writ ten along w ith dat a . this allow s v e ry ver s a t ile ope ra tio n , includin g ?a ny leng th ? fra m es. ? up to fo ur sla v e se lect in put/outp u t s with select ab le po lar i ty an d fle x ib le usag e. ? su pp or t s dm a tr an sf er s: spin tr an sm it an d re ce ive fu n ctio n s wo rk wit h the s yst em dma c o ntroller . remark: t e xa s instr u m ent s ssi an d na tiona l m i cr owir e mod e s a r e n o t su ppo rted . 8.20 i2c-b us interface th e i 2 c-bus i s bidirec t ional for inter-ic contro l using o n ly two wires: a se ria l clock line ( s cl ) an d a seria l dat a lin e (sda). each de vice is reco gnized b y a u n iqu e ad dr ess an d can ope ra te as either a r e ceiver -o nly de vice ( e .g., an l c d dr iver ) or a tra n smitter with the cap a bility to both receive and s e nd information (s uc h as me mory). t r ansmitters and/or r e ceiver s ca n o per ate in eithe r m a ster or sl a v e mo de, de pe ndin g o n whe t h e r th e chip ha s to initiate a dat a tr an sf er o r is o n ly ad d r e sse d. t h e i 2 c is a m u lti-m a ste r bu s an d ca n be con t r o lle d by m o r e th an o ne bu s ma ste r conn ecte d to it. th e i2c-b u s fun c tio n s a r e fixed- pin fu nctio n s and m u st be ena bled th rou g h the switch ma tr ix o n the op en -dr a in p i ns pio0_2 2 an d pio0_2 3. 8.20 .1 fea tures ? sup p o r t s st a nda rd a nd fast m ode with da t a ra te s o f up to 4 00 kbit/s. ? su pp or t s fa st -m od e plu s wit h bit rates up to 1 mbit/s . ? fa il-safe o per ation : whe n the po we r to an i 2 c- bus de vice is switch ed o f f, the sda a nd scl pins conn ecte d to th e i 2 c- bu s ar e floa tin g a n d d o no t d i st ur b th e bu s. ? ind epe nde nt master , slave, an d mon i to r function s. ? su pp or t s bo th m u lt i-m a s te r a n d mu lti- m a st er wit h slav e fu nct i on s. ? multiple i 2 c sla v e add re sses su pp or te d in ha rdwa re. ? one sla v e ad dr ess ca n b e sele ctively qu alified with a b i t mask or an ad dr ess ra nge in o r de r to re sp on d to m u ltiple i 2 c bu s ad dr esse s. ? 1 0 -b it a ddr essing sup por ted with so f t war e assist. ? support s smbus. ? su pp or te d by o n - ch i p rom a p i.
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 33 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 8.21 c_can con t r o lle r are a ne two r k (can) is the d e finition o f a hig h pe rfor man c e co mmu nication p r oto c o l fo r ser i al d a t a co mmu nication . t he c_ can contr o ller is de sig ned to pr ovide a full imp l eme n t a tio n o f th e can pr otocol acco rd in g to the can s p ecifi c a t io n v e rsion 2.0b. t he c_can controller can build powerful loc a l ne tworks w ith low - c o st multiplex wiring by supporting distributed real -time control with a high lev e l of reliability . th e c_ can fun c tion s ar e m o vab l e fun c tio n s an d a r e assign ed to pin s th ro ug h the switch m a t r ix. do n o t co nn e c t c_ can fun c t i on s t o th e op en - d r a in p i ns pio 0 _2 2 an d pio 0 _2 3. 8.21 .1 fea tures ? con f o rms to pr otocol ve rsio n 2.0 p a rt s a a nd b. ? support s bit rate of up to 1 mbit /s. ? su pp or t s 32 m e s s a g e o b je ct s . ? each mess age o b ject has i t s own identifier mask . ? pr ovides pr ogr am mab l e fifo mo de ( c o n caten a tion of messag e obj e ct s) . ? pr ovides maskab l e inter r u p t s . ? sup p o r t s disab led auto matic retr ansmission ( d ar) m ode for tim e -tr i gge re d can applications. ? pr ovides pr ogr am mab l e loo p -b ack m ode for se lf- t est o per ation . 8.22 pwm/timer/motor con t rol sub system th e sct i mer / pwm s (s t a te co nfigur ab le t i me r/pulse wid t h m odu lator s ) and th e ana log pe r i ph er als su p p o r t m u lt iple ways of inter c onn ecti ng their inpu t s a nd ou tput s and of in te rfacing to th e pin s a n d th e dma co ntro ller . using th e hig h ly flexible a nd p r o g r a mma ble con nection schem e makes it e a sy to config ur e var i o u s su bs yst em s f o r m o to r c o n tr o l an d comp lex tim i ng an d tra c king a p p lica t io ns. s p e c ifically , the inp u t s to the sct s a nd the trig ge r inp u t s o f the adcs an d dma a r e sele cte d th ro ugh th e inpu t mu x which of fer s a cho i ce o f ma ny possible sou r ces fo r ea ch inpu t or tr igg e r . sct outp u t s a r e a s sign ed to pin s th ro ug h th e swit ch m a tr ix allo win g for m a ny pin o u t so lut i on s. 8.22 .1 sctimer/pwm subsy stem th e sct i m e r / pwms can be config ure d to bu ild a pwm controller with multiple output s by p r og ra mmin g th e ma tch and m a tchrel oad r e g i ster s to con t r o l the ba se fr eq uen cy a nd the d u ty cycle o f ea ch sct i mer / pwm ou tp ut. mo re com p le x wavefor m s tha t sp an mu ltip le coun ter cycle s or ch ang e be havio r acro ss or within cou n ter cycles ca n be generated using the st ate cap a bilit y built into the sct i mer/pwms. combining the pwm functions with the analog functions, the pwm output can react to control signals like comparator outputs or the adc interrupts. the sct ipu adds emergency shut-down functions and pre-processing of controlling events. for an overview of the pwm subsystem, see figure 12 ? pwm-analog subsystem ? . for high-speed pwm functionality, use only outputs that are fixed-pin functions to minimize pin-to-pin differences in output skew. see also table 22 ? sct output dynamic characteristics ? . this reduces the number of pwm outputs to five for each large sct.
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 34 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 8.22 .2 t imer controlle d subsy stem th e time rs, th e a n a l og co mpo nen t s , a n d th e dma ca n b e con f ig ur ed to form a su bsystem tha t can r un in dep end en tly of th e main p r o c e s sor und er the contro l o f the sct s and an y e v e n t s tha t a r e g ene ra te d by th e a/d co nver ters, th e co mp ar ator s, th e sct o u tpu t the m selves, o r th e exter nal pin s . a/d conver si ons can be tr igge re d by th e tim e r o u tpu t s, the com p a r a t o r outp ut s or b y even t s fro m exte rn al pin s . da t a can be tran sfer re d from the adcs to me mor y using th e dma contr o ller , an d the dma tra n sfers can be tr igge re d by the adcs, th e co mp ar ator o u tpu t s, or b y the time r outp u t s. fo r an o v ervie w of th e subsyste m, see f i gur e 13 ? subsystem with timers, switch matrix, dma, and analog components ? . fi g 12 . pw m-ana lo g su bs y s te m input mux switch matrix switch matrix temp sensor vdda divider voltage reference trigger adc0/adc1 analog in interrupts acmp0 acmp1 acmp2 acmp3 outputs sct ipu analog in timer0 ma tch/ ma tchreload sct0 outputs timer1 ma tch/ ma tchreload sct1 outputs timer2 match/ matchreload sct2 outputs timer3 ma tch/ ma tchreload sct3 outputs 8 x pwm out 8 x pwm out 6 x pwm out 6 x pwm out sct0/1/2/3 digital signal from/to pins analog signal from/to pins digital signal internal analog signal internal analog peripheral digital peripheral threshold crossing aaa-010873 4
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 35 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 8.22 .3 sct im er/ pw m in th e large c onfiguration (sct0 /1) remark: f o r a pplicatio ns tha t r equ ire e x act timing o f the sct ou tp ut s ( f or e x a m ple pwm), assign the output s only to fix e d-pin fu nc tions to ens u re that th e ou tp ut sk ew is n ear ly the sam e fo r all o u tput s. 8.22 .3 .1 fe at ures the following feature list sum m ar izes the con f ig ur ation for the two lar ge sct s . ea ch la rg e sct has a comp an ion sma ll sct (see se ctio n 8 .22.4 ) with fewer inpu t s a nd ou tp ut s and a re du ce d fe at ur e se t. ? each sct support s : ? 1 6 ma tch/captu r e r egister s ? 1 6 even t s ? 1 6 st ates ? match register 0 to 5 support a fractional component for the dither engine f i g 1 3 . s u b sy stem with timers , switc h matrix, dma, an d an alog c o mp on en t s temp sensor vdda divider vol t age reference acmp0 acmp1 acmp2 acmp3 timer0 (sct0) timer1 (sct1) timer2 (sct2) timer3 (sct3) input mux outputs outputs trigger adc0/adc1 dac sct ipu analog in input mux dma switch matrix switch matrix analog in interrupts nvic dac_shutoff digital signal from/to pins analog signal from/to pins digital signal internal analog signal internal analog peripheral digital peripheral threshold crossing aaa-010874 4
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 36 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller ? 8 inpu t s an d 10 o u tpu t s ? dma supp or t ? cou n ter / time r featur es: ? co nfigur ab le as two 16 -b it cou n ter s or one 3 2 - b it co unter . ? counters clocked by sys tem clock or selec t ed input . ? co nfigur ab le as up coun ters or u p - d o w n cou n ter s . ? co nfigur ab le nu mbe r of match and ca ptur e re giste r s. up to 16 m a tch a n d cap t u r e re gis ter s tot a l. ? up on ma tch cr ea te th e following even t s : sto p , halt, limit co unter or ch an ge cou n ter dir e c tion ; to gg le ou tp u t s; c r e a t e an in te rr up t; ch an g e the s t at e. ? co unter va lue can b e loa ded in to ca ptur e re giste r trig ger ed b y ma tch o r in pu t/ou tp ut to ggle . ? pwm fe atur es: ? co unter s can b e used in co njun ctio n with ma tch r e g i ster s to tog g le ou tp ut s and cr eate time -pr o p o r t io ne d pwm sign als. ? up to eig h t sin g le- e d ge o r du al-e dg e co ntro lled pwm ou tp ut s with up to e i ght in de pen de nt d u ty cycle s whe n co nfigu r ed as 3 2 - b it time rs. ? event crea tion featu r es: ? t he follo win g cond itio ns define a n even t: a coun te r ma tch con d ition, an in put (o r output) c o ndition s u c h as an rising or fa lling edge or level, a combination of match an d/ or in pu t/ ou tp ut co n d itio n . ? even t s can o n ly have a n ef fe ct while the cou n ter is ru nnin g . ? se lected even t s can lim it, ha lt, st a r t, o r sto p a coun te r or ch ang e it s d i re ction . ? even t s trig ge r st ate ch an ges, o u tpu t togg les, in te rr up t s , and dm a tra n sactions. ? m a tch reg i ste r 0 can be used as an a u toma tic limit. ? in b i -d irection al mod e , e v ent s ca n be e n a b led b a sed o n th e coun t di rection . ? ma tc h e v e n t s ca n b e he ld un til an ot he r qu a lifyin g ev en t o c c u r s . ? s t ate con t r o l featur es: ? a st ate is d e fine d by the se t of even t s tha t ar e allo we d to hap pe n in th e st ate. ? a st ate chan ge s into an othe r st ate as resu lt of an e v e n t. ? ea ch event ca n be a s sig ned to o ne or mor e st ates. ? s t at e v a r i ab le a llows se q u e n c i ng acro ss multip le co unte r cycles. ? dither eng ine. ? in te gr at ed w i th an in p u t pr e - p r o c e ssin g un it (sct ip u) to co m b in e or d e la y inp u t ev en t s . inp u t s an d ou tp ut s on the sct i m e r 0 /pwm and sct i me r1/pwm ar e co nfigur ed as follows: ? 8 in put s ? 7 inpu t s . each inp u t e x ce pt in put 7 can sele ct one of 2 3 so ur ce s fro m an in put multiplex e r . ? one input connected directly to the sc t pll for a high-speed dedicated clock input.
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 37 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller ? 1 0 outpu t s ( s o m e o u tput s ar e co nn ecte d to multiple lo cations) ? t hr ee ou tp ut s co nn ecte d to exte rn al pins thro ug h th e switch matr ix as movab l e funct ions. ? f i ve o u tpu t s con nected to exter nal pi ns thr o u gh the switch ma tr ix a s fixed- pin funct ions. ? t w o outpu t s con n e c ted to the sctipu to samp le or la tch in put even t s . ? one o u tpu t conn ected to th e othe r lar g e sct ? f our outpu t s con n e c ted to o ne small sct ? t w o outpu t s con n e c ted to ea ch adc tr igg e r in put 8.22 .4 s t ate - co nfigurable t imers in the sm all con figuration (sct2/3 ) remark: f o r a pplicatio ns tha t r equ ire e x act timing o f the sct ou tp ut s ( f or e x a m ple pwm), assign the output s only to fix e d-pin fu nc tions to ens u re that th e ou tp ut sk ew is n ear ly the sam e fo r all o u tput s. 8.22 .4 .1 fe at ures the following feature list summarizes the config uration for the two small scts. each small sct has a companion large sct (see section 8.22.3 ) with mo re in put s an d ou tp ut s and a d i th er e ngin e. ? each sct support s : ? 8 match/ca ptur e re giste r s ? 1 0 even t s ? 1 0 st ates ? 3 inpu t s an d 6 ou tp ut s ? dma supp or t ? cou n ter / time r featur es: ? co nfigur ab le as two 16 -b it cou n ter s or one 3 2 - b it co unter . ? counters clocked by bus clock or selec t ed input . ? up cou n ter s or up- do wn co unter s. ? co nfigur ab le nu mbe r of match and ca ptur e re giste r s. up to 16 m a tch a n d cap t u r e re gis ter s tot a l. ? up on ma tch cre a te the followin g even t s : in terrupt, st op, limit time r or cha n g e d i re ctio n; tog g le o u tput s; ch ang e st ate. ? co unter va lue can b e loa ded in to ca ptur e re giste r trig ger ed b y ma tch o r in pu t/ou tp ut to ggle . ? pwm fe atur es: ? co unter s can b e used in co njun ctio n with ma tch r e g i ster s to tog g le ou tp ut s and cr eate time -pr o p o r t io ne d pwm sign als. ? up to six sing le- edg e or d u a l -ed g e con t r o lle d pwm o u tpu t s with inde pen de nt d u ty cycles if c o nfigured as 32-bit t imers. ? event creation features:
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 38 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller ? t he follo win g cond itio ns define a n even t: a coun te r ma tch con d ition, an in put (o r ou tp ut ) c o n d i tion , a co mb in atio n o f a m a tch a n d /o r an d inp u t/o ut pu t co nd itio n in a sp ecifie d st ate. ? se lected even t s can lim it, ha lt, st a r t, o r sto p a coun te r . ? even t s con t r o l st ate chan ge s, outpu t s , inter r u p t s , a nd dma re que st s. ? m a tch reg i ste r 0 can be used as an a u toma tic limit. ? in b i -d irection al mod e , e v ent s ca n be e n a b led b a sed o n th e coun t di rection . ? ma tc h e v e n t s ca n b e he ld un til an ot he r qu a lifyin g ev en t o c c u r s . ? s t ate con t r o l featur es: ? a st ate is d e fine d by e v ent s th at ca n t a ke pla c e in th e st a t e wh ile th e coun te r is ru nn ing . ? a st ate chan ge s into an othe r st ate as resu lt of an e v e n t. ? ea ch event ca n be a s sig ned to o ne or mor e st ates. ? s t at e v a r i ab le a llows se q u e n c i ng acro ss multip le co unte r cycles. ? in te gr at ed w i th an in p u t pr e - p r o c e ssin g un it (sct ip u) to co m b in e or d e la y inp u t ev en t s . inp u t s an d ou tp ut s on the sct i m e r 2 /pwm and sct i me r3/pwm ar e co nfigur ed as follows: ? 3 in put s. ea ch inpu t sele ct s one of 2 1 so ur ce s fro m a pin m u ltiplexe r . ? 6 ou tp u t s ( s o m e o u t p u t s ar e co nn ec te d to m u ltip le lo cat i on s) ? thr ee ou tp ut s co nn ecte d to exte rn al pins thro ug h th e switch matr ix as movab l e funct ions. ? t h r ee ou tp ut s co nn ecte d to exte rn al pins thro ug h th e switch matr ix as fixe d-p i n funct ions. ? t w o o u tp u t s co nn ec te d to th e sct i p u t o s a m p le or la tch in pu t ev en t s . ? fo u r o u tp u t s co nn ec te d to th e ac co mp an yin g lar g e sc t ? t w o outpu t s con n e c ted to ea ch adc tr igg e r in put 8.22 .5 sct input pro cessin g unit (sctipu) th e sctipu allo ws to blo c k or pr op aga te sig n a l s to inp u t s of th e sct und er th e co ntro l of an s c t ou tp u t. usin g th e sct ipu in th is wa y , allo ws sig n a l s t o be b l oc ke d fro m e n t e r i ng the sct inp u t s for a ce rt a i n amo u n t of tim e , fo r examp l e while the y ar e known to be inv a lid. in ad dition , the sctipu can ge ne rate a com m on sign al fro m se ve ra l com b ine d inp u t sources t h at can be selec t ed on all sct i npu t s . such a me ch anism can b e useful to cr ea te a n ab or t sign a l that st op s all timers . 8.22 .5 .1 fe at ures th e sct i pu pr e-p r o c e sse s inp u t s to the s t a t e-co nfigur ab le t i me rs (sct) . ? f o u r ou tp ut s cr ea te d fr om a se le ctio n of in pu t tr an sition s. each ou tp ut ca n be u s e d as ab o r t inp u t t o the sc t s or fo r an y ot he r ap plic at ion wh ich r e q u i re s a co lle ctio n of multiple sct input s to trigge r an identic a l s ct response.
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 39 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller ? fo ur r e g i ster s to in dicate wh ich sp ecific inp u t so ur ce s cause d th e ab ort inp u t to the sct s . ? fo ur a dditio nal ou tput s wh ich ca n be sam p le d at ce rt a i n tim e s a n d la tch e d at ot he rs b e fore bein g ro uted to sct inpu t s . ? nine a bor t in put s. an y comb inatio n of the a bor t in put s ca n tr igg e r the d edica te d abo rt in put of e a ch sct . 8.23 qu adrature enco der interface (qei) a qua dr atur e en co der , also kn own as a 2- ch an nel incr eme n t a l e n code r , conver t s a ngu lar dis p la ce m e n t in to t w o pu lse s i gn als . by m o nitor i ng bo th th e num ber of p u lses and th e r e lative pha se o f the two sign als, the user cod e ca n tr ack the po sitio n , di rection of ro t a tion, a nd ve locity . in add ition, a third cha nne l, or ind e x signa l, ca n b e u s e d to re se t th e p o sition cou n ter . th e qu adr atur e en co de r inter f a c e decod es th e dig i t a l pulse s fro m a qua dr atur e e n code r whee l to in te gr ate po sition o v er ti me a nd de te rm ine dir e ction o f r o t a tion . in a ddition , the qei can cap t u r e the ve locity of th e encod er wh eel. 8.23 .1 fea tures ? t r acks encoder posit i on. ? incre m en t s /d ecre men t s de pe ndin g on d i re ction . ? pr ogr amm able fo r 2 ? or 4 ? position cou n ting . ? v e locity ca ptur e using b u ilt- i n tim e r . ? v e locity co mp ar e fu nction with ?le s s th an? inter r u p t. ? use s 32 -b it re gis ter s for p o s itio n an d ve loc i ty . ? t h r e e p o s itio n- co mp ar e re gis te r s with in te rr up t s . ? index counter f o r re v o lution counting. ? in de x co mp ar e re gis te r w i th int e r r u p t s . ? can com b ine i nde x an d po sition inter r up t s to pr od uce an in te rr up t for who l e an d p a rtial revolution di s p lacement. ? digit al filter with prog r a mm a b le d e la ys fo r en co de r inp u t s i gn als . ? can a c cep t d e code d signa l inpu t s ( c lo ck an d dir e ctio n) . 8.24 analog-to -digit al con verter (adc) th e adc su ppo rt s a re so lution of 12 bit and fast con v ersio n r a tes of up to 2 m s a m ple s /s. seq u e n ces of a n a l og- to- d igit a l co nver sio n s ca n be tr igg e re d by mu ltip le sour ces. po ssible trig ge r so ur ce s ar e inter n a l con n e c tion s to othe r on- chip pe rip h e r als such as the sct an d analog comp arator outp ut s, external pins, and the arm txev interrupt. th e adc supp or t s a var i ab le clo c kin g sche me with clo c kin g synchr on ou s to th e system clock o r ind e p end ent, a s yn ch ro nou s clocking for h i gh -spe ed con v e r sion s. th e adc includ es a har dwar e thr e shold co mp ar e f u n c t i on wit h ze ro -cr o ssin g de te ctio n . th e thre shold cr ossin g inter r u p t is conn ected in ternally to the sct input s for t i ght timing con t r o l be twee n the adc an d the sct s.
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 40 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 8.24 .1 fea tures ? 12-bit successiv e approximat io n an alog -to- dig i t a l conver ter . ? 12 - b it co nv er sio n ra te of 2 m h z. ? inp u t m u ltiplexin g amo ng 12 pins and up to 4 inter n a l sou r ces. ? in te rn al so ur ce s a r e t h e te m p e r atu r e s e n s o r vo lt ag e, in te rn al re fe re nc e volt a g e , co re volt a ge r egu lator o u tpu t , an d vdda/2 . ? t w o con f ig ur ab le co nver sio n sequ en ce s with inde pen de nt tr igge rs. ? optiona l a u tom a tic hig h /low th re sh old com p a r ison a n d zer o - c r o ssing d e tectio n. ? powe r- down mo de a nd low- powe r op era t ing mo de. ? me asur eme n t ran g e vrefn to vrefp ( t yp ica lly 3 v ; no t to exceed vdda volt a g e lev e l). ? bur s t conve r sion m ode for sin g le o r multip le inpu t s . ? synchr ono us or a s ynch ron o u s op er ati on. asyn ch ro nou s op er ation m a ximizes flexibility in c h oosing the ad c c l ock frequency , synchron ous mode minimiz e s trigger la te ncy an d can eli m ina t e u n cer t ainty and jitter in r e spo n se to a trigg e r . 8.25 digit a l-to-ana log con verter (dac) th e dac su pp or t s a re solution of 1 2 bit s . con v e r sion s ca n b e trig ger ed by an exter nal pin in put or a n inter nal time r . th e dac includ es an op tio n a l a u toma tic ha rd wa re shu t - o f f fea t ure wh ich for c es th e dac output volt age to zero while a h i gh lev e l on the exte rn al dac_shut off pin is detected . 8.25 .1 fea tures ? 1 2 -b it d i git a l- to- ana log con v e r ter . ? su pp or t s dm a. ? inter n a l time r or p i n exter nal trig ger fo r st age d, jitter - fr ee dac conv ersion sequencing. ? autom a tic h a rd war e sh ut-o f f tr igg e r ed by an e x ter n a l p i n. 8.26 analog comp arator (acmp) th e lpc15 x x includ e four an alog co mp ara t ors with se ve n select a b le in put s ea ch fo r ea ch p o sitive o r n ega tive in pu t cha nne l. t w o an alog inp u t s are co mmo n to all fou r com p a r a t o r s. inter n a l volt a g e in put s includ e a volt ag e lad der refe ren c e with sele ct a b le volt a ge sup p ly so ur ce , t h e t e m p er at ur e se nso r or t h e in te rn al vo lt a g e re fe re nc e. th e a n a l og inpu t s to the comp ar ator s ar e fixed - pin fun c tion s an d mu st be ena bled thr o u gh the switch matrix. the outputs of each analog comparator are internally connected to the adc trigger inputs and to the sct inputs, so that the result of a voltage comparison can trigger a timer operation or an analog-to-digital conversion.
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 41 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 8.26 .1 fea tures ? seven s e lect able input s . fully config ura b le o n eithe r th e po sitive side or th e ne gative in put ch an nel. ? 3 2 -st a ge volt ag e lad der inter nal r e fer ence for se lect abl e vo lt age s o n each comp a r ato r ; co nfigur ab le on e i th er p o sitive o r ne gative comp ar ator i npu t. ? v o lt age la dd er sou r ce volt ag e is sele ct able fr om an e x te rna l pin or th e 3.3 v a n a l og volt age supply . ? 0. 9 v in te rn al ba n d g a p re fe re nc e volt a g e se lect a b l e as eit h e r po sit i ve or n e g a tive in put on e a ch co mp ar ator . ? t e mp er atur e sensor vo lt age se lect ab le as e i th er p o sitive o r ne ga tive inp u t on ea ch co m p ar a t or . ? v o lt age la dd er can b e sep a r a tely powered down for applic a tio ns on ly re qu irin g th e comp a r ato r fu nction. ? ind i vid ual comp ar ator o u tput s ca n b e co nne cte d in tern ally to the sct an d adc trig ge r in put s or the e x te rn al pins. ? sep a r a te in te rr upt for e a ch co mp ar ator . ? pin filter in clu ded o n ea ch co mp ara t o r ou tput. ? th re e pr op aga tion de lay va lues ar e pr ogr am mab l e to o p timize be twe en spee d an d po we r co ns um p tio n. ? relax a tion oscillator circ uitr y output for a 555 sty le time r operation us in g c o mp arator b l ocks 0 an d 1. 8.27 t e mperature sensor th e temp era t u r e se nsor tra n sdu c e r uses an in tr insic p n - j un ction d i od e re fe re nce and o u tput s a ct a t volt a g e ( c o m ple m en t t o absolu te t e mpe r a t u r e ) . t he ou tput vo lt ag e var i es inver s e l y with device temp era t ure with a n ab so lut e acc u r a c y o f be tte r th an 5 ? c ov er th e fu ll t e m p er at ur e ra ng e ( ? 40 ? c to +105 ? c) . t h e tem p er a tur e se ns or is on ly ap p r o x im at ely lin ea r wit h a slig ht cu r v at ur e. t h e ou tp u t v o lt a g e is m e as ur ed ove r d i f fe r e n t r ang es of tem per atur es and fi t with lin ear -le a st-squ are lines. af ter po wer- up , th e te mpe r a t u r e sensor o u tpu t must be a llowed to settle to it s st ab le valu e b e for e it can b e used a s an a c cu rate adc in put. fo r an a c cu ra te m easur eme nt of the te mpe r at ur e se ns or b y t h e adc , t h e ad c m u st b e con f ig ur ed in sing le- c h ann el bu rst m ode . th e last valu e of a nine -con ve rsion (or mor e ) b u rst pro vides an a c cur a te r e sult. 8.28 in ternal volt ag e reference th e inter nal volt a ge re fere nce is a n accu ra te 0 . 9 v an d is th e ou tp ut o f a low vo lt age b a n d g ap circuit. a typ i cal va lue a t t amb = 25 ? c is 0.90 5 v . the in te rn al vo lt ag e re fe ren c e ca n b e used in the follo wing ap plication s : ? whe n the supp ly volt a ge v dd is kn own accur a tely , th e inter n a l volt a g e r e fer ence can b e used to re du ce the o f fset er ro r e o o f the adc cod e outpu t. th e adc er ror cor r e c tion th en incr ease s the accur a cy o f temp er atur e se nsor vo lt age o u tpu t me asur eme nt s .
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 42 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller ? wh en t h e adc is a c c u r a t e ly ca libr a t e d , t h e in te rn a l vo lt ag e re fe re nc e ca n b e us ed t o me asur e the po we r sup p ly volt a g e . th is r equ ire s calibr a tion by r e cor d in g th e adc cod e of th e inter nal volt a ge r e fer ence at dif f er ent powe r su pp ly level s yieldin g a d i f f er en t adc cod e va lue fo r ea ch supp ly volt ag e level. in a p a r t icu l ar ap plication , th e in te rn al vo lt age refe ren c e ca n be me asur ed a nd the a c tua l power su pply volt ag e can b e de te rm ined fr om th e store d calib ra tio n valu es. the ca libr a tion va lues can be stor ed in the eeprom for easy access. af ter po we r- up , th e in te rn al volt a g e re fe re nce must be allo we d to se ttle to it s st ab le val ue b e for e it can b e used a s an adc r e fer e n c e vo lt age in pu t. f o r an a ccu ra te m e asu r em e n t of th e in te rn al volt a g e r e fer e nce b y t h e adc , th e adc m u st b e co nfigur ed in sing le- c h a n nel bu rst mo de . th e l a st value o f a nin e - c o n ver s i on (o r mo re) b u rst pro v ides an a c cur a te r e sult. 8.29 mu lti-rate t i mer (mrt) the multi-rate t i mer (mr t) provides a repetiti v e interrupt timer with fou r ch ann els. each cha nne l ca n be pr og ra mme d with an inde pen de nt time in te rval, an d each cha nne l o per ates inde pe nde ntly fr o m th e othe r chan ne ls. 8.29 .1 fea tures ? 2 4 -b it in te rr upt timer ? fo ur cha n n e ls in de pen den tl y coun tin g do wn fr om ind i vidua lly set va lues ? rep eat an d one -sho t in te rr upt mod e s 8.30 w i nd owed w a tc hdog t i mer (wwdt) th e watch dog time r r e set s th e co ntro ller if so f t w a re fails to periodic a lly serv ice it w ithi n a p r og ra mma ble time wind o w . 8.30 .1 fea tures ? inter n a lly r e set s ch ip if no t p e rio d ically re load ed d u r i ng the p r og ra mma ble time- o u t pe r i od . ? optiona l win dowed ope ra tio n re quir e s re load to o c cur betwee n a minim u m an d ma xim u m time pe rio d , b o th pr og ra mmab l e. ? optiona l wa rni ng inter r u p t ca n be g ene ra te d at a pr ogr amm able time prio r to watchdo g time- out. ? ena b le d by sof t war e bu t req u ir es a h a r d war e r e set or a watchdo g r e set/inter ru pt to be d i sa bled . ? incor r e c t feed seq u e n ce ca uses re se t or inter r u p t if en able d . ? flag to indicate watchdog reset. ? pr ogr amm able 24- bit tim e r with inter nal p r escale r . ? sele ct able time p e r i od fro m (t cy( wdcl k) ? 25 6 ? 4) to (t c y ( w dclk ) ? 2 24 ? 4) in multiples of t c y ( w dclk ) ? 4. ? the wwdt is clocked by the dedicated wa tchdog oscillator (w dosc) running at a fixed frequency.
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 43 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 8.31 repetitive inte rrupt (ri) timer th e re petitive inter r u p t time r pr ovide s a fre e - r u nnin g 48 -bit coun te r which is com p a r e d to a sele ct a b le valu e, gen er ating a n inter r up t whe n a match occur s . any b i t s o f the timer / co mp ar e ca n be m a ske d such th at th ey d o no t contr i bute to the ma tch d e tectio n. th e re petitive inter r u p t time r can be used to crea te an inter r upt th at rep e a t s at p r ed eter mine d inter v als. 8.31 .1 fea tures ? 48 - b it co un te r ru nn in g fro m th e m a in clo c k. co un te r can be fr ee -r unn ing o r ca n be r e set wh en an rit inter r u p t is ge ner ated . ? 48- b it co mp ar e va lue . ? 4 8 -b it com p a r e ma sk. an inter r u p t is gen er ated whe n the coun ter valu e equ als th e co m p ar e v a lu e, af te r m a skin g . this allow s for co m b ina t io ns no t po ss ible with a s i mple comp are. 8.32 system tick timer the arm cortex-m3 includes a system tick timer (systic k) that is inte nded to generate a de d i ca ted sy st ick exc e p tio n at a fi xe d time inter v al (typically 10 ms) . 8.33 real-t ime clock (rtc) th e r t c r e side s in a se p a ra te, a lways- o n vo lt age dom ain with batter y b a ck- u p . th e r t c us es an independent 32 k hz osc illator , also loc a ted in the alwa y s-on volt age domain. 8.33 .1 fea tures ? 3 2 -b it, 1 hz r t c co unter and a sso cia t e d match re gister for alar m ge ner ation . ? se p a ra te 16 - b it hig h - r e so lu tio n / w ak e- up t i me r clo cke d at 1 kh z fo r 1 m s r e s o lu tio n with a mor e that on e minu te m a ximum time -ou t p e r i od. ? r t c a l ar m and high -r esolu t io n/wake- up ti mer time -o ut each ge ne ra te in dep en den t in te rr upt re que st s. eith er time -ou t can wa ke u p th e p a r t from a n y of the l o w p o wer mo de s, includi ng deep power -d own.
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 44 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 8.34 clock generation fi g 14 . c lo ck g e ne ra ti on system oscillator watchdog oscillator irc system oscillator irc irc usb pll usbpllclksel (usb pll clock select) system clock divider sysahbclkctrln (ahb clock enable) cpu, system control, pmu memories, peripheral clocks systick peripheral clock divider arm core systick ioconclkdiv clock divider iocon digital glitch filter arm trace clock clock divider arm trace usart peripheral clock divider fractional ra te generator usart[n:0] wwdt clkoutsela (clkout clock select a) usb 48 mhz clock divider usb watchdog oscillator irc system oscillator usbclksel (usb clock select) clkout pin clock divider clkout pin system clock system pll irc system oscillator watchdog oscillator mainclkselb (main clock select b) mainclksela (main clock select a) syspllclksel (system pll clock select) main clock irc system oscillator rtc oscillator n system oscillator irc sct pll sctpllclksel (sct pll clock select) sct async adc clock divider adc adcasyncclksel (clock select) 32 khz rtc oscillator 32 khz clkoutselb (clkout clock select b) aaa-010875
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 45 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 8.35 power do mains th e lpc15 xx p r o v id e two ind epe nd ent po we r d o ma ins that allo w th e bu lk o f th e de vice to h a ve powe r re moved wh ile main t a ini ng op er ation o f the r t c a n d the b a ckup reg i ster s. th e vba t pin sup p lies po we r on ly to the r t c d o ma in. the r t c req u ir es a minim u m of p o wer to op er ate, wh ich can be supp lied b y a n exte rn al ba tter y . th e de vice cor e po we r (v dd ) is used to o per ate the r tc wh ene ve r v dd is pr esen t. the r efo r e, ther e is n o po we r d r ain fr om the r t c batter y when v dd is a nd v dd >= vba t + 0.3 v . 8.36 in tegrated oscillators the lpc15x x include the follo wing independent os cillators: the sys tem osc illator , the internal rc osc illator (irc), the w a tchdog os cillator , and the 32 khz r t c os cillator . each os cillator c a n be us ed for multiple purposes. following reset, the lpc15xx op erates from the internal rc os cillator until sof t w a re switche s to a dif f er ent clock sou r ce. the ir c allo ws the system to op er ate with out any e x ter n a l cr yst a l an d the bo otloa der co de to op er ate at a kn own freq ue ncy . see f i gur e 14 for an overview of the lpc15xx clock generation. f i g 1 5 . p o w e r di st ri bu tio n real-time clock backup registers wake-up control regulator 32 khz oscillator always-on/rtc power domain main power domain rtcxin vba t vdd rt c x o u t vdd vss to memories, peripherals, oscillators, plls to core to i/o pads adc temp sense acmp dac internal voltage ref adc power domain vdda vssa lpc15xx ultra low-power regulator wakeup aaa-010876
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 46 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 8.36 .1 inte rna l rc oscillat or the irc can be used as the clock that drives the system pll and then the cpu. in addition, the irc can be selected as input to various clock dividers and as the clock source for the usb pll and the sct pll (see figure 14 ) . t h e no m i na l ir c f r e q u e n cy is 12 m h z . upo n powe r - up, an y chip r e set, o r wake- up fro m de ep po wer- do wn mod e , the l p c1 5xx u s e the irc a s the clock so urce . sof t war e ca n later switch to on e of th e othe r availa ble clock sources. 8.36 .2 syste m osci llator the s ystem oscillator can be used as a s t able and accurate c l oc k s o urc e for the c pu, with or w ithout using the pll. for usb applic ations, us e the s yst em oscillator to provide the clock source to usb pll. the system oscillator operates at frequenc ies of 1 m hz to 25 mhz. this frequency can be b oosted to a hig h e r fr eq uen cy , up to the m a ximum cpu o per ating fr equ en cy , by th e sys tem pll. the sy stem oscillator has a w a ke -up time of approx i mately 500 s. 8.36 .3 w atch dog osc illator the low-power w a tchdog os cillato r can be used as a clock source that directly driv es the cpu , the watc hdog timer , or the clkou t pi n. the watc hdog osc illa tor nominal frequenc y is f i xe d at 50 3 k h z . t h e fr eq ue n cy spr e ad o v e r p r o c e s s i ng a n d t e m p er at ur e is ? 40 %. 8.36 .4 rtc osci llator the low-power rtc osc illator provides a 1 hz clock and a 1 khz clock to the rtc and a 32 khz clock output that can be us ed to obtain the main clock (see figure 14 ) .t h e 32 kh z os cillator output c a n be observed on the c l kout pin to allow trimmi ng the r t c os cillator withou t in te rfer ence fro m a pr ob e. 8.37 system pll, us b pll, and sct pll th e lpc15 x x co nt a i n a th re e ide n tica l pl ls fo r ge ner ating the syste m clo c k, th e 48 mhz usb clock, a nd an asyn ch ro nou s clock fo r th e adcs and sct s . the syste m pll is u s ed to cre a te th e main clo c k. t he sct and u sb plls cr ea te d e d i ca te d clocks fo r the as ynchronous ad c, t h e asynchrono u s sct clo ck inp u t, an d th e usb. remark: t he usb pll is availa ble o n p a rt s lpc15 49/48 /4 7 on ly . th e pll a c cep t s a n inpu t clock fr equ ency in th e ra nge of 1 0 mhz to 25 m h z. t he inp u t frequency is multiplied up to a high frequency with a c u rren t controlled osc illator (cco). th e multip lier can b e an in te ger va lue fro m 1 to 32. the cco op er ates i n th e ra nge o f 1 5 6 m hz to 32 0 m hz. t o su pp or t this fr equ en cy ra nge , an add itio na l d i vid e r kee p s the cco with in it s fre que ncy r a n ge while the pl l is p r ovid ing the d e sire d outpu t fre q u ency . th e ou tp ut d i vider ca n be set to d i vid e by 2, 4 , 8 , or 16 to pr odu ce th e ou tp ut clock. t he pll o u tpu t fre que ncy m u st be lo wer tha n 100 mhz. si nce th e minim u m ou tp ut divider valu e is 2 , it is insur ed tha t the pll o u tpu t ha s a 5 0 % d u ty cycle . th e pll is tu rn ed of f a nd byp a ssed follo win g a ch ip re set. sof t war e ca n en able th e pll later . the p r og ra m mu st config ure and activa te the pll, wait fo r the pll to lock, an d then co nne ct to th e pll as a clock source. the pll settling time is 100 ? s.
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 47 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 8.38 clock output the lpc 1 5xx feature a c l ock output function that routes the internal os cillator output s, the pl l ou tp ut s , o r th e m a in clo ck an o u t p u t pin wher e the y can be obser ved dir e ctly . 8.39 wake-up process the lpc15x x begin operation by using the 12 mhz irc os cillato r as the c l ock source at p o wer - up and whe n awaken ed fr om deep p o wer - d o wn mo de. this mecha n ism allo ws chip operation to resume quickl y . if the applic ation uses the sy stem oscillator or the pll, sof t ware must enable these c o mp onent s and wait for them to st abilize. only then can the sys tem us e the p l l and s ystem oscillator as a clock source. 8.40 power co ntrol th e lpc15 x x su pp ort vario u s power contro l fe atur es. th er e are four spe c ia l mod e s o f p r oce s sor power reduction: slee p mod e , dee p - s le ep m ode , power - down mo de, an d dee p powe r - down mo de . th e cpu clo c k ra te ca n also be con t r o lle d as nee de d by cha ngin g clock sou r ces, r e con f iguring pll va lues, a n d / o r alter i ng the cpu clo c k divide r value. this power cont r o l m e chan ism allo ws a tra de- of f of po wer ve rsus p r o c e s sin g spe ed b a sed o n app lication r equ ire m en t s . in ad dition, a r egister is pr ovide d for shu t tin g down the clo cks to in div i du al on -c hip p e r ip he ra ls. t h is re g i ste r allo ws fin e - tu n in g of p o we r con s u m ption by elimin ating all dyna mic power use in any pe rip her als that ar e n o t re quir e d for th e app lica t ion. selected p e r i phe ra ls ha ve th eir o w n clo c k divide r wh ich pr ovides a ddition al po we r contr o l. 8.40 .1 power profiles th e po we r consum ption in active a n d sle ep mo des ca n be o p timized for th e app lication thr o u gh simple cal l s to th e po we r pr ofile. the p o wer co nfigur ation r o u t in e configu r e s the lp c15 xx fo r on e of th e fo llow i ng p o w er m o de s: ? de fa ult m o d e co rr es po nd in g to po we r co nf igu r a tio n af t e r r e se t. ? cpu performance mode co rresponding to optimiz e d processing cap a bility . ? ef ficie ncy mod e co rr espo ndin g to op tim i ze d bala n ce of cur r e n t con s u m ption a nd cpu p e rfor ma nce. ? l o w-cur r e n t m ode corr espo ndin g to l o west po wer con s u m ption . in ad dition , the po wer p r ofile in clu d e s ro utin e s to select the optima l pl l se ttin gs for a g i ve n system clock an d pll in put clo ck an d to easily se t the con f ig ur ation op tions fo r dee p- s le ep an d po we r- do wn m ode s. remark: whe n using th e usb, co nfigur e the l p c1 5xx in defau l t mo de. 8.40 .2 sleep mode whe n sleep m ode is enter ed , the clock to the cor e is sto ppe d. re su mption fr om the slee p mo de d oes no t ne ed an y spe c ia l se que nce bu t r e - ena bling th e clo c k to th e arm cor e . in sle e p m o de , ex ecu tio n of in str u c tio ns is su sp en ded u n til either a re se t or inter r u p t o c cur s . per i ph era l fu nctio n s co ntinue ope ra tio n du ring sle ep m ode a nd can g ene ra te in te rr upt s to ca use the pr ocessor to r e sume e x ecution . slee p mod e elimin ates dynam ic po we r us ed b y t h e p r o c e s s o r it se lf, by m e m o ry sys te ms a n d r e la te d co ntr o ller s , an d by in te rn al buses.
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 48 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 8.40 .3 deep-s leep m ode in dee p -sle ep mo de, the l p c1 5xx is in slee p- mo d e and all pe rip her al clocks an d all clock so ur ce s a r e o f f e xce pt fo r th e irc. t h e i rc ou tp ut is disa b l ed u n le ss th e irc is sele ct ed a s inp u t to th e watch dog tim e r . in ad dition a ll ana log b l ocks ar e shu t d o wn an d th e flash is in st and-by mode. in deep-sleep mode, the application can keep the watchdog oscillator a nd the bod circuit run n in g fo r self-time d wa ke-u p an d bod p r o t e c tio n . th e lpc15 x x ca n wake up fro m de ep -slee p mod e via rese t, se lecte d gpio pin s , a watchdo g timer in terr up t, an in te rr up t ge ner ating usb por t a c tivity , an r t c inter r u p t, o r an y inte r r u p t s th at th e u sar t , spi, o r i2 c in te rf ac es ca n c r e a t e in d e e p - s le ep m o de . t h e usar t wake- u p r e q u ir es th e 32 khz mo de, th e syn c h r o nou s mo de , or th e ct s in te rr upt to be set up. dee p - s le ep mo de saves po we r an d allows fo r shor t wake- u p time s. 8.40 .4 power-down mode in power - d o wn mo de, th e lpc15 x x is in slee p- mod e an d all pe riph er al clocks an d all clock sources are of f ex cept for w a tchdog os cillator if selec t ed. in addition all analog b l ocks an d th e fla s h are sh ut d o wn. in po we r- do wn m ode , the a ppli c a t io n ca n keep th e bod circuit ru nnin g fo r bod pr otecti on. th e lpc15 x x ca n wake up fro m power - d o wn mod e vi a rese t, se lected gpio pin s , a watchdo g timer in terr up t, an in te rr up t ge ner ating usb por t a c tivity , an r t c inter r u p t, o r a n y in te rr up t s that the usar t , spi, o r i2 c in te rfaces can cre a te in power-do wn mode. t h e us ar t wa ke -u p re q u ir es th e 32 k h z m o de , th e syn ch ro no u s m o de , o r th e ct s int e rrupt to be set up. powe r- down mo de r e d u ces p o wer co nsump t io n comp ar ed to deep -slee p mo de at th e e x p ense o f lon ger wa ke -u p times. 8.40 .5 deep power-do w n mo de in deep power-down mode, power is shut of f to the entire chip except for the w akeu p p i n and th e always-on r tc po we r- do main . th e lpc15xx ca n wa ke up fro m de ep p o wer - do wn mod e via th e w a keup pin or a wa ke -u p signa l g e n e ra ted by th e r tc in te rr upt. th e lpc15 x x ca n be b l ocke d fro m e n ter i ng dee p po we r- do wn m ode b y setting a lo ck bit in th e pmu b l oc k. b l ock i ng t h e de e p po we r- do wn m o de e n a b l es th e ap plic at ion to k e e p the watchd og timer or the bod r unn ing a t all times. if the w akeup pin is used in th e application, an ex ternal pull-up resist or is required on the w akeup pin to hold it high while the p a rt is in deep power-do wn mode. pul ling the w akeup pin low wakes up the p a rt from deep power-down mode. in addition, pull the reset pin high to prevent it from floating while in deep power-down mode.
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 49 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 8.41 system control 8.41 .1 rese t reset has four sources on the lpc15xx: the reset pin, the watchdog reset, power-on reset (por), and the brownout detection (bod) circuit. the reset pin is a sch m itt trig ge r in put p i n. asse rtion of chip re set by a n y sour ce, on ce the ope ra tin g volt a g e att a in s a us ab le lev e l, st a r t s th e irc a n d initialize s the flash contr o ller . whe n th e inter n a l rese t is r e mo ved, th e pr oc essor b egin s e x e c u t in g at add re ss 0, wh ich is initially th e re se t vector m app ed fro m th e bo o t blo ck. at th at p o in t, all of th e pr oc es so r a nd pe rip her al r egister s ha ve bee n in itialized to p r e deter min ed valu es. in deep power-down mode, an external pull-up resistor is required on the reset pin. the reset pin is operational in active, sleep, deep-sleep, and power-down modes if the reset function is selected through the switch ma trix for pin pio0_21 (this is the default). a low-going pulse as short as 50 ns executes the reset and thereby wakes up the part to its active state. the reset pin is not fu nctiona l in de ep po wer - do wn mod e and m u st b e pulled high externally w h ile the p a rt is in dee p po we r- do wn m ode . 8.41 .2 browno ut detec tion th e lpc15 x x includ es b r o w n - o u t d e tection ( b od) with two levels fo r mo nitor i ng the volt a ge on th e v dd pin. if this v o lt age falls below one of two selected le ve ls, th e bod a s ser t s a n inter r u p t sig nal to th e nvic. t h is sign al can be ena bled fo r inter r u p t in th e interrupt enable r e g i st er in th e nv ic to ca us e a c p u in te rr upt. altern atively , sof t wa re can mo nitor th e sig nal b y read ing a d edicated st a t u s r egister . t w o th resh old leve ls can be sele cted to cau s e a fo rced r e set of th e ch ip. 8.41 .3 code s ecurity (code re ad protection - crp) crp pro v ides dif f er ent le ve ls o f secu rity in th e s yst em so th at ac ces s to the on-chip flash a nd use o f the ser i al wire deb u g ger (swd) and in -system pr og ram m ing ( i sp) ca n be re st rict ed . p r o g r a m m i ng a s p e c ific p a tt er n in to a ded icated flash location invokes crp . iap com m an ds a r e n o t af fe cted by the crp . fig 16. r eset pin configuration 9 66 uhvhw ddd 9 '' 9 '' 9 '' 5 sx (6' (6' qv5& */,7&+),/7(5 3,1
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 50 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller in ad dition , isp e n try the exter n a l p i ns ca n be d i sa ble d with out en ablin g crp . fo r d e t a ils, see the lpc 1 5 xx us er m an u al . th er e ar e th re e levels of co de read pr otection : 1. crp 1 d i sa b l es ac ce ss t o th e ch ip v i a th e s w d a n d allo ws p a rtia l f l ash u p d a te ( e xclu din g fla s h se ctor 0) u s in g a limited set of th e isp comma nd s. this mod e is u s e f u l when crp is r equ ire d an d flash fi e l d u pda te s are ne ede d b ut all sector s ca nno t b e era s ed. 2. crp 2 d i sa b l es ac ce ss t o th e ch ip v i a th e s w d a n d on ly a llo ws f u ll fla s h er a s e an d u pda te u s ing a r edu ce d set o f the isp co mman d s. 3. ru nn in g a n ap p licat ion with level cr p3 selected , fu lly d i sa ble s a n y acce ss to the chip via the swd p i ns a nd the isp . this mod e ef f e ct ively disables i sp over rid e using isp p i n as wel l . if ne ce ssa r y , th e app licati on mu st pr ovide a flash u pda te mecha n ism u s in g iap calls or using a ca ll to th e r e invoke isp co mma nd to e nab le flash up da te via the usar t . in ad dition to the thr ee crp le ve ls, samp ling of th e isp pin s for va lid user co de can b e d i sa bled . fo r de t a ils, see th e lpc15xx u s er ma nu al . c aution if level three code read protection (crp3) is selected, no future factory testing can be performed on the device.
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 51 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 8.42 emulation and debugging deb ug fun c tion s ar e inte gra t ed into the arm co rte x - m 3. ser i al wir e de bu g fu ncti ons ar e sup por ted in a ddition to a st an da rd jt ag b o u nda ry scan . th e arm cor t ex-m 3 is con f ig ur ed to supp or t up to fou r br ea kp oint s an d two watch poin t s. the reset pin selects between the jtag boundary scan (reset = low) and the arm swd debug (reset = high). the arm swd d e b ug po rt is disab l ed while the lpc15 x x is in res e t. t o pe rfor m bo und ar y sca n testin g, fo llow the s e step s: 1 . er ase any user co de r e sidin g in fla s h . 2. power up the part with the reset p i n pu lled high e x ter n a lly . 3. w a it for at leas t 250 ? s. 4. pull the reset pin low e x ter n a lly . 5 . per f or m b o u nda ry scan ope ra tio n s. 6. once the boundary scan operations are completed, assert the trst p i n to en ab le th e swd debug mode, and release the reset pin (pull high). remark: the jtag interface cannot be used for debug purposes. 9. limiting values t a ble 9. l i miting v a lues in accorda n ce with th e ab solute ma ximum rating system (iec 6013 4). [1] symbol parameter conditions min max unit v dd suppl y vol t a ge (3.3 v) [2 ] ? 0.5 v dda v v dd a ana log supp ly vo lt age ? 0.5 + 4.6 v v re f refe rence volt ag e on pin vref p_dac_vdd cmp ? 0.5 v dda v on pin vrefp_adc ? 0.5 v dda v v ba t battery sup p ly volt age ? 0.5 + 4.6 v v i inpu t vol t ag e 5 v tolera nt i/o pin s ; onl y val i d when the v dd( io) su pply volt ag e i s pr ese n t [3 ] [4 ] ? 0.5 + 5.5 v on i2 c o pen -d rain pi ns pio0_22 , pio0_ 2 3 [5 ] ? 0.5 + 5.5 v 3 v tolera nt i/o pin wi th out over-volt age protection . appl ies to pi o0_ 12. [6 ] ? 0.5 v dda v usb_dm, usb_dp pins ? 0.5 v dd + 0. 5 v v ia ana log in put vo lt a g e [7 ] [8 ] [9] ? 0.5 +4.6 v v i( xt al) cr yst al input volt age [2 ] ? 0.5 + 2.5 v v i( rtc x) 32 khz o scilla to r in put vo lt a g e [2 ] ? 0.5 +4.6 v i dd suppl y curren t per suppl y pi n - 100 ma i ss groun d current per groun d pin - 100 ma
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 52 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller [1] t he following app lies t o the limiting values: a) t h is prod uct includ es cir c uitr y specif ically designed fo r the pr otection o f it s in ternal devices from the damaging ef fect s o f ex cess ive st atic char ge. nonethe less, it is sugg es ted that co nvent ional pr ecautions be t ak en to avoid applying g r eater than the r ated maxi mu m. b) para meters are valid over opera t ing te mperatur e rang e unless other wise specifi ed. all volt ages are w i th r esp ect to v ss unless other wise n oted. [2] maximum/minimum voltage above the maximum operating voltage (see table 11 ) and below ground that can be ap plied for a short time ( < 10 ms) to a device without leading to irr ecover able failure. f ailur e includes the loss of r eli ability a nd sh orter lifetime o f the device. [3] a pplies to all 5 v tole rant i/o pins except tr ue open- drain pins pio0_22 an d pio0_ 23 and exce pt the 3 v toleran t pin pio0_12 . [4] inclu ding the vo lt age on output s in 3-st ate mo de. [5] v dd( i o ) present or not present. c ompliant with the i 2 c- bus st an dard. 5.5 v can b e applied to this pin when v dd (io ) is power ed dow n. [6] a pplies to 3 v to ler ant pins pio0_12. [7] a n adc input volt age ab ove 3. 6 v can b e applied fo r a short ti me without leading to immediate, unr ecover able f ailure. accumu lat e d exposure to e l evated volt ages at 4.6 v must be less than 10 6 s tot a l over the lifetime of the device. applying an elevated volt age to th e adc input s for a long tim e af fe ct s the r eliabili ty of the device and reduces it s lifet i me. [8] if the comp arator is configu r ed with the common mo de inp ut v ic = v dd , the other comp arato r input can be up to 0.2 v above or be low v dd w i thou t af fe cting the hysteresis r ange of the comp a r ator function. [9] it is recommended to connect an o v er volt age p r otectio n diod e between the analog in put pin and the volt age supply pin. [10] dep endent on p ackage type. [11] human body model: equivalent to dischar ging a 100 pf capacitor through a 1.5 k ? series resistor. 10. thermal characteristics th e aver ag e ch ip jun c tion te mpe r atu r e, t j ( ? c) , can b e ca lculated u s ing the follo win g e qua tio n: (1 ) ? t amb = a m bie n t t e m p er at ur e ( ? c), ? r th (j- a ) = the p a ckage ju nction- to-a mbi ent th er mal re sist a n ce ( ? c/ w) ? p d = sum of inter n a l a nd i/o power dissip a t io n the internal power dissipation is the product of i dd and v dd . the i/o power dissipation of the i/o pins is often small and many times can be negligible. however it can be significant in some applications. i la tch i /o l a t c h- up cu rre n t ? (0.5v dd( io) ) < v i < (1 .5 v dd( io) ); t j < 125 ? c - 100 ma t stg sto r a ge temperature [1 0] ? 65 +15 0 ? c t j ( max ) ma ximum j unction tempe r a t u r e - 150 ? c p t o t( p a ck ) to t a l p o wer dissip a tion (pe r p a ckage) based o n p a ckage he at tran sfer , n o t d e vice pow er co nsumption -1 . 5 w v esd electrostatic discharge voltage human body model; all pins [11] -5k v t a ble 9. l i miting v a lues ?contin ued in accorda n ce with th e ab solute ma ximum rating system (iec 6013 4). [1] symbol parameter conditions min max unit t j t amb p d r th j a ? ?? ? ?? + =
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 53 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller t a ble 10. th erm a l r esist an ce value (c/w): 15 % symbol parameter conditions typ unit lq fp4 8 ? ja thermal resist ance jun cti on-to-ambie nt jedec (4.5 in ? 4 in) 0 m/s 6 4 ? c/w 1 m/s 5 5 ? c/w 2. 5 m/s 5 0 ? c/w 8- layer (4.5 in ? 3 i n ) 0 m/s 9 6 ? c/w 1 m/s 7 6 ? c/w 2. 5 m/s 6 7 ? c/w ? jc thermal resist ance junc ti on-to-case 13 ? c/w ? jb thermal resist ance jun c ti on-to-boa rd 16 ? c/w lq fp6 4 ? ja thermal resist ance jun cti on-to-ambie nt jedec (4.5 in ? 4 in) 0 m/s 5 1 ? c/w 1 m/s 4 5 ? c/w 2. 5 m/s 4 1 ? c/w 8- layer (4.5 in ? 3 i n ) 0 m/s 7 5 ? c/w 1 m/s 6 0 ? c/w 2. 5 m/s 5 4 ? c/w ? jc thermal resist ance junc ti on-to-case 13 ? c/w ? jb thermal resist ance jun c ti on-to-boa rd 17 ? c/w lq fp1 0 0 ? ja thermal resist ance jun cti on-to-ambie nt jedec (4.5 in ? 4 in) 0 m/s 4 2 ? c/w 1 m/s 3 7 ? c/w 2. 5 m/s 3 4 ? c/w 8- layer (4.5 in ? 3 i n ) 0 m/s 5 9 ? c/w 1 m/s 4 8 ? c/w 2. 5 m/s 4 4 ? c/w ? jc thermal resist ance junc ti on-to-case 12 ? c/w ? jb thermal resist ance jun c ti on-to-boa rd 17 ? c/w
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 54 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 1 1 . s t atic characteristics t a ble 1 1 . s t a tic ch ara c teristics t am b = ? 40 ? c to + 1 05 ? c, un less otherwise sp ecified. symbol parameter conditions min typ [1] max unit v dd sup p ly volt age (core an d exte rnal rai l) [2] 2.4 3 .3 v dda v v dda an alo g su pply volt ag e 2 .4 3.3 3 .6 v v re f referen c e vo lt a ge o n pin vrefp_dac_vddcmp 2.4 - v dda v on pin vrefp_adc 2 .7 - v dda v v ba t ba ttery suppl y vol t a g e 2 .4 3.3 3 .6 v i dd sup p ly current active mode ; code while( 1){} e x ecuted from flash ; system clock = 12 mhz; default mo de; v dd = 3. 3 v [3] [4] [5] [7] [8] -4 . 3 - m a system c l ock = 12 mhz; low-current mode; v dd = 3.3 v [3] [4] [5] [7] [8] -2 . 7 - m a system clock = 72 mhz; default mode; v dd = 3.3 v [3] [4] [7] [8] [10] - 19.3 - ma system c l ock = 72 mhz; low-current mode; v dd = 3.3 v [3] [4] [7] [8] [10] -1 8 - m a sl eep mode ; system clock = 12 m h z ; default mode; v dd = 3.3 v [3] [4] [5] [7] [8] -2 . 1 - m a system c l ock = 12 mhz; low-current mode; v dd = 3.3 v [3] [4] [5] [7] [8] -1 . 5 - m a system clock = 72 mhz; default mode; v dd = 3.3 v [3 ] [4] [10] [7] [8] -8 . 0 - m a system c l ock = 72 mhz; low-current mode; v dd = 3.3 v [3 ] [4] [10] [7] [8] -7 . 3 -ma i dd sup p ly current d eep-sl eep mode ; v dd = 3 .3 v ; t am b =2 5 ? c [3 ] [4] [11] - 310 380 ? a t am b =1 0 5 ? c - - 620 ? a i dd sup p ly current po wer-dow n mo de; v dd = 3. 3 v t am b =2 5 ? c [3 ] [4] [11] - 3.8 8 ? a t am b =1 0 5 ? c - - 163 ? a i dd sup p ly current d eep po wer-dow n mo de; v dd = 3 . 3 v ; vba t = 0 or vba t = 3.0 v r t c o s ci llator runn ing t am b =2 5 ? c [3] [12] [13] -1 . 1 1.3 [14] ? a t am b =1 0 5 ? c- - 1 5 ? a r t c os cil l a to r i n pu t gr ou n d e d ; t amb =25 ? c [3 ] [12] - 560 - na
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 55 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller i ba t ba ttery suppl y curren t d eep po wer-dow n mo de; v dd = v dd a = 3. 3 v ; vba t = 3 .0 v [13] 0-n a v dd a nd v dda ti ed to g r ound ; vba t = 3. 0 v [13 ] 1- ? a s t andard port pins config ured as digit a l pins, reset ; see figure 17 i il low - level in put cu rrent v i = 0 v ; on -ch i p pul l-up resistor d isabl ed -0.5 10 [14] na i ih high -l evel in put current v i =v dd ; on-ch ip pul l-down resistor disabled -0 . 5 1 0 [1 4] na i oz off - st ate outpu t current v o =0 v ; v o =v dd ; on-chi p p u ll -u p/down resi stors disa bled -0 . 5 1 0 [1 4] na v i in put vo lt age v dd ? 2 . 4 v ; 5 v tole rant p i ns e xcept pio0_12 [1 6] [18] 0- 5v v dd ? 2 . 4 v ; on 3 v tol e rant pin pio0_12 0- v dda v dd = 0 v 0 - 3 .6 v v o ou tp ut vol t ag e o u tput acti ve 0 - v dd v v ih high -l evel in put volt age 0.7 v dd -- v v il low -level in put vo lt age - - 0.3v dd v v hys hysteresis volt ag e 2 .4 v < = v dd < 3 .0 v 0 .3 0 - - v 3. 0 v < = v dd < = 3.6 v 0.3 5 - - v v oh high -l evel ou tp ut volt age i oh =4 m a v dd ? 0. 4 - - v v ol low -level ou tp ut volt age i ol =4 m a - - 0 . 4 v i oh high -l evel ou tp ut current v oh =v dd ? 0.4 v 4 - - m a i ol low -level ou tp ut current v ol =0 . 4 v 4 - - ma i oh s high -l evel sho r t-circuit ou tp ut curren t v oh =0v [1 9] -- -45ma i ols low - level short-circuit ou tp ut curren t v ol =v dd [1 9] -- 5 0 m a i pd pu ll-do wn current v i = 5 v 10 50 150 ? a i pu pu ll-up curre nt v i =0v ; ? 10 ? 50 ? 85 ? a v dd lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 56 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller v i in put vo lt age v dd ? 2. 4 v [16] [18] 0- 5 . 0 v v dd = 0 v 0 - 3 .6 v v o ou tp ut vol t ag e o u tput acti ve 0 - v dd v v ih high -l evel in put volt age 0.7 v dd -- v v il low -level in put vo lt age - - 0.3v dd v v hys hysteresis volt ag e 2 .4 v < = v dd < 3 .0 v 0 .3 0 - - v 3. 0 v < = v dd < = 3.6 v 0.3 5 - - v v oh high -l evel ou tp ut volt age i oh = 2 0 ma; 2.7 v < = v dd < 3. 6 v v dd ? 0. 4 - - v i oh = 1 2 ma; 2.4 v < = v dd < 2. 7 v v dd ? 0. 4 - - v v ol low -level ou tp ut volt age i ol =4 m a - - 0 . 4 v i oh high -l evel ou tp ut current v oh =v dd ? 0.4 v ; 2.7 v < = v dd < 3 . 6 v 20 - - ma v oh =v dd ? 0.4 v ; 2.4 v < = v dd < 2 . 7 v 12 - - ma i ol low -level ou tp ut current v ol = 0 .4 v 4 - - ma i ol s low - level short-circuit ou tp ut curren t v ol =v dd [1 9] -- 5 0 m a i pd pu ll-do wn current v i =5v [2 0] 10 50 150 ? a i pu pu ll-up curre nt v i =0v [2 0] ? 10 ? 50 ? 85 ? a v dd lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 57 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller [1] t ypical ratings are n ot guara nteed. th e va lues listed are for r oom temper ature ( 25 ? c) , nominal supply volt ages. [2] f or usb oper ation: 3.0 v ??? v dd ? 3.6 v . [3] t amb =2 5 ? c. [4] i dd measur ement s wer e perfo rmed with all p i ns config ured as gpio ou tput s driven low and pull-up resistors disab l ed. [5] irc enabled; system oscillator disabled; system pll disable d . [6] s ystem o s cillator ena bled; i rc disab l ed; system p l l disabled. [7] b od disabled. [8] a ll per iph erals d i sabled in t he sys ah b c lkctrl 0/1 registers. pe ripher al clo c ks t o usar t , cl k o ut , and iocon disabled in system configuration block. [9] irc enabled; system oscillator disabled; system pll en abled . [10] irc disabled; system oscill ator enabled; system pll en abled . [1 1] all oscillato r s and analog blocks turne d of f: use a p i p owe r_mo de_co nfigur e() with mode p ar ameter set to deep _ s l e ep or powe r _down and per ipher al p aramet er set to 0xff . [12] wakeup pin pulled high externally. v ih high -l evel in put volt age 1.8 - - v v il low -level in put vo lt age - - 1.0 v v hys hysteresis volt ag e 0 .3 2 - - v z ou t ou tp ut imp edan ce 28 - 4 4 ? v oh high -l evel ou tp ut volt age 2.9 - - v v ol low -level ou tp ut volt age - - 0.18 v i oh high -l evel ou tp ut current v oh =v dd ? 0.3 v [2 2] 4.8 - - m a i ol low - level ou tp ut current v ol = 0 .3 v [2 2] 5.0 - - m a i ol s low - level short-circuit ou tp ut curren t d r ive low ; p ad conn ected to g r ound - - 125 ma i oh s high -l evel sho r t-circuit ou tp ut curren t d r ive high; p ad conn ecte d to g r ound - - 125 ma osci ll ator p i ns v i(xt al) cryst a l i npu t volt age o n pin xt al in ? 0.5 1 .8 1.95 v v o( xt a l ) cryst al ou tp u t v o l t ag e o n p i n xt a l o u t ? 0.5 1 .8 1.95 v v i(rt cx) 32 khz oscil l ator inpu t volt age on p i n r t c xin [2 3] ? 0.5 - 3.6 v v o( rtcx ) 32 khz o s ci llator output volt age on p i n r t c x ou t [2 3] ? 0.5 - 3.6 v pin cap a cit a nce c io in put/output cap a cit a nce p ins with ana log an d digi t a l fu nct i on s [2 4] -- 7 . 1 p f i 2 c-bus pins (pio0_ 22 and pio0_23 ) [2 4] - - 2.5 pf p ins with dig it a l fu ncti ons onl y [2 4] -- 2 .8pf t a ble 1 1 . s t a tic ch ara c teristics ? c ont inued t am b = ? 40 ? c to + 1 05 ? c, un less otherwise sp ecified. symbol parameter conditions min typ [1 ] max unit
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 58 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller [13] r t c running or not run ning. [14] cha r acterized on sa mples. not tested in pr oduction . [15] low -curren t mode pwr_low_curr e n t sele cted w hen ru nni ng the se t_power routine in the powe r pro files. [16] inclu ding volt age on output s in tri-st ate mode. [17] v dd supply volt age mu st be p r esent. [18] t r i-st ate output s go into t r i- st ate mode in deep power- down mo de. [19] allow ed as long a s the cur r ent limit does not exceed the maximum cu rren t allowed b y the device. [20] pull-up and pull-down currents are measured across t he weak internal pull-up/pull-down resistors. see figure 17 . [21] t o v ss . [22] t he p ara meter values specif ied ar e simulated and abso l ute values. [23] t he inp ut volt age of the r t c oscillator is limite d as f ollows: v i(rt cx) , v o(r t cx) < max(vb a t , v dd ). [24] inclu ding bondin g p ad cap acit ance . fi g 17 . p in in pu t/o u tp ut cu rre nt meas ure men t aaa-010819 + - pin pio0_n i oh i pu - + pin pio0_n i ol i pd v dd a a
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 59 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 1 1 .1 power consumption powe r me asur eme n t s in active , sle e p , a nd de ep- sleep mod e s wer e pe rfor me d un der the follow ing conditions: ? con f ig ur e all pin s as gpio with p u ll- up r e sisto r disab l ed in the iocon blo c k. ? con f ig ur e gpio pin s as outp u t s u s in g the gpio dir re gister . ? w r ite 1 to the gpio clr re giste r to dr ive th e outp u t s l o w . conditions: t am b = 25 ? c; active mode entered executing code whi le(1){ } from flash; a l l peripher als disabled in the sys ahbc lkctrl 0/1 r egist er s; all peripher al clocks disabled; in ternal pull- up resistor s disable d; bo d disabled; low-curr ent mode. 1 mhz - 6 mhz: i rc enabled; pll disable d. 12 mhz: irc enabled; pll disabled. 24 mhz to 72 mh z: ir c enabled; pll en abled. fig 18 . a ctive mo de : t ypica l su pp ly c u rr ent i dd vers u s su p p ly volt ag e v dd aaa-011384 2.4 2.6 2.8 3 3.2 3.4 3.6 0 4 8 12 16 20 v dd (v) i dd dd i dd (ma) (ma) (ma) 12 mhz 24 mhz 48 mhz 60 mhz 72 mhz 36 mhz 6 mhz 1 mhz
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 60 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller conditions: v dd = 3.3 v ; active mode e ntered e x ecuting co de wh ile(1){ } from fla s h; all peripher als disabled in the sys ahbc lkctrl 0/1 r egist er s; all peripher al clocks disabled; in ternal pull- up resistor s disable d; bo d disabled; low-curr ent mode. 1 mhz - 6 mhz: i rc enabled; pll disable d. 12 mhz: irc enabled; pll disabled. 24 mhz to 72 mh z: ir c enabled; pll en abled. fig 19 . a ctive mo de : t ypica l su pp ly c u rr ent i dd vers u s tem p er atur e conditions: v dd = 3.3 v ; sleep mode enter ed from fl ash; all per ip heral s d i sabled in the sysa hbclkctrl0/1 reg i sters; all pe ri p heral cl ock s dis a bl ed; i nternal pul l-up resi stors dis ab l ed; bod disabled; low-curr ent mode. 1 mhz - 6 mhz: i rc enabled; pll disable d. 12 mhz: irc enabled; pll disabled. 24 mhz to 72 mh z: ir c enabled; pll en abled. fig 20 . sle ep mo de : t ypica l su pp ly c u rr en t i dd ver sus tem p er atur e fo r differe nt sys tem cloc k fr eq uen cies aaa-011385 -40 -10 20 50 80 110 0 4 8 12 16 20 temperature (c) i dd dd i dd (ma) (ma) (ma) 12 mhz 24 mhz 48 mhz 60 mhz 72 mhz 36 mhz 6 mhz 1 mhz aaa-011386 -40 -10 20 50 80 110 0 2 4 6 8 temperature (c) i dd dd i dd (ma) (ma) (ma) 72 mhz 48 mhz 36 mhz 24 mhz 12 mhz 6 mhz 1 mhz 60 mhz
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 61 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller conditions: b o d disable d; all oscillator s a nd analog blocks disabled. use api power_mode_configure() with mode p a rameter se t to deep_sleep and peri pheral p a rameter set to 0xff . fig 21 . dee p-slee p mod e : t y p i cal s u p p ly cu rre nt i dd v e rsus tempera t ure for diffe r ent s u p p l y vo lt ag es v dd conditions: bod disabled; all oscill ators and analog blocks disabled; v dd = 2 .4 v to 3.6 v . use api power _mode_configure( ) with mode p aramete r se t to power_ down and peripher al p arameter set to 0xff . fi g 22 . p ow er-d ow n mo de : t y pi ca l su pp ly c u rr ent i dd vers u s tem p er atur e fo r differe nt s u p p l y vo lt ag es v dd aaa-01 1234 -40 -10 20 50 80 110 280 300 320 340 360 380 400 temperature (c) i dd dd i dd (a) (a) (a) 3.6 v 3.3 v 3.0 v 2.7 v 2.4 v aaa-011235 -40 -10 20 50 80 110 0 20 40 60 80 temperature (c) i dd dd i dd (a) (a) (a)
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 62 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller vba t = 0 v . f i g 2 3 . d e e p p o w e r-d o w n mo de : t y pic a l su pp ly c u rre nt i dd ve rsu s temp eratu r e for di ffere nt su pp ly vo l t a g es v dd vba t = 3.3 v ; v dd float ing. f i g 2 4 . d e e p p o w e r-d o w n mo de : t y pic a l ba tte ry su pp ly c u rren t i ba t vers u s temp er atur e aaa-011236 -40 -10 20 50 80 110 0 1 2 3 4 temperature (c) i dd dd i dd (a) (a) (a) 2.4 v 3.3 v 3.6 v aaa-011333 -40 -10 20 50 80 110 0 1 2 3 4 temperature (c) i bat bat i ba t (a) (a) (a)
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 63 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 1 1 .2 coremark dat a conditions: v dd = 3.3 v ; active mode; all peripher als excep t one uar t an d the sct disabled in the sysahbclkctrl0/1 regi ster; i n ternal pul l-u p resi stors enab l ed; bod disabl ed . measu r ed with keil uv isio n v . 4.73.0.0, c compiler v .5.03.0.76 . fig 25 . co remark s cor e conditions: v dd = 3.3 v ; t amb = 25 ? c; active mode; all per iphe rals except on e uar t and the sct dis abled in the sysahbclkctrl0/1 regi sters ; sys tem cloc k deri v ed from the irc; s y s t em oscillator disabled; internal pul l- up re sisto r s enabled; bod disabled. measured with k e il uv ision v .4.73.0.0, c comp iler v .5.03.0 .76. fi g 26 . a cti ve mo de : co remar k po wer c o n su m pti o n i dd aaa-011746 0 12 24 36 48 60 72 2.35 2.4 2.45 2.5 2.55 2.6 2.65 system clock frequency (mhz) cm score cm score cm score efficiency cpu default/low current aaa-011747 0 12 24 36 48 60 72 0 5 10 15 20 25 30 system clock frequency (mhz) i dd dd i dd (ma) (ma) (ma) default cpu efficiency low-current
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 64 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 1 1 .3 peripheral power consumption th e sup p ly cu rr en t p e r per iph e r a l is me asur ed a s th e dif f er ence in supp ly cu rr ent b e twe e n the p e r i phe ra l b l ock e nab led a nd the p e ri phe ra l b l ock d i sa bled in th e sysahbclkcfg and pdr uncfg (for analog block s ) regis t ers. all other bloc ks are dis a bled in both r egister s a nd no co de accessing the p e ri phe ra l is executed . me asur ed o n a typica l sample at t amb =2 5 ? c. unles s noted otherwis e, th e sys tem osc illator and pll are r unn ing in b o th me asur eme n t s . th e supp ly cur r e n t s a r e sho w n fo r system clock fr equ encie s of 12 mhz a n d 7 2 mhz. t abl e 12 . p o w er c o n sum pti o n fo r in di vid u al ana l o g an d d i g i t a l bloc ks peripheral typical supply current in ma notes n/a 12 mhz 72 mhz irc 0 .00 8 - - system oscillator running; pll off; independent of main clock frequency. system oscilla to r at 12 mhz 0 .22 0 - - irc run n ing ; pll o f f; inde pen dent of ma in clock freq uency . w a tchd og oscil l ator 0.00 2 - - s ystem o scilla to r run n ing; pll of f; i ndep endent o f main clo ck frequ ency . bod 0 .045 - - independen t of ma in clock freq uency . ma in pll - 0.085 - - u sb pll 0.100 sct pll 0 .1 10 c l kou t - 0 .005 0.01 ma in clock divid ed by 4 in th e clkou t div re gister . r o m - 0.015 0.02 - gpio + pin interrupt/ p att e rn match - 0 .55 0 .60 g pio pin s con f ig ured as ou tpu t s and se t to l o w . direction a nd pin st ate are ma int a in ed if the gpio is disabled in the sysahbclkcfg re gister . sw m - 0.04 0.29 - input mux 0 .05 0 .30 ioco n - 0 .06 0 .40 - sct i mer0/pw m - 0 .18 1 .10 - sct i mer1/pw m - 0 .19 1 .10 - sct i mer2/pw m - 0 .13 0 .70 - sct i mer3/pw m - 0 .16 0 .90 - sct i p u 0 .02 0 .1 r t c - 0.01 0.05 - mr t - 0.03 0.10 - wwdt - 0 .01 0 .10 main clock s e lect ed as clock source for the wdt . ri t 0 .07 0 .20 qei 0 .12 0 .80 i2c0 - 0 .02 0 .12 - spi0 - 0.03 0.3 - spi1 - 0.01 0.28 -
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 65 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 1 1 .4 electrical p i n characteristics usa r t 0 - 0 .02 0 .15 - usa r t 1 - 0 .02 0 .16 - usa r t 2 - 0 .02 0 .15 - c _ can - 0.50 3.00 u s b - 0.10 0.50 c o mp arator acmp0/1 / 2 / 3 - 0.01 0.03 - adc0 - 0 .05 0 .33 - adc1 - 0 .04 0 .33 - tempe r ature sensor - 0 .03 0 .03 i nternal volt age re fe rence/ba nd ga p - 0 .03 0 .04 d a c - 0.02 0.09 - d m a - 0.36 1.5 c r c - 0.01 0.08 - t abl e 12 . p o w er c o n sum pti o n fo r in di vid u al ana l o g an d d i g i t a l bloc ks ? c ontinued peripheral typical supply current in ma notes n/a 12 mhz 72 mhz conditions: v dd = 3.3 v ; on pin pio0_24. fig 27. high-drive output: typical high-level output voltage v oh versus high-level output current i oh aaa-011257 0 10 20 30 40 50 2.7 2.8 2.9 3 3.1 3.2 3.3 i oh (ma) v oh oh v oh (v) (v) (v) -40 c 25 c 90 c 105 c
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 66 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller conditions: v dd = 3.3 v ; on pins pio0_ 22 and pio0_23. fi g 28 . i 2 c-bu s pi ns (h ig h cu rre n t s ink ): t y pi c a l lo w - le ve l ou tpu t c u rre n t i ol ver sus low - leve l o u tpu t volt age v ol conditions: v dd = 3.3 v ; st andar d port pins and high-d r ive pin pio0_24. fig 29 . t y p ical low - l eve l ou tpu t c u rr ent i ol versu s lo w -level ou tpu t vo lt age v ol aaa-011258 0 0.1 0.2 0.3 0.4 0.5 0 10 20 30 40 50 v ol (v) i oh oh i ol (ma) (ma) (ma) -40 c 25 c 90 c 105 c aaa-01 1263 0 0.1 0.2 0.3 0.4 0.5 0 2 4 6 8 10 i ol (ma) v ol ol v ol (v) (v) (v) -40 c 25 c 90 c 105 c
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 67 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller conditions: v dd = 3.3 v ; st andar d port pins. fig 30 . t y p ical high-leve l ou tpu t v o lt a g e v oh v e rs us high-lev el o u tp ut sou r c e c u r r en t i oh conditions: v dd = 3.3 v ; st andar d port pins. fig 31 . t y p ical pu ll-up cur r en t i pu ver su s in pu t v o lt a g e v i aaa-01 1276 0 3 6 9 12 2.7 2.9 3.1 3.3 v oh (v) i oh oh i oh (ma) (ma) (ma) -40 c 25 c 90 c 105 c aaa-011277 0 1 2 3 4 5 -80 -60 -40 -20 0 v i (v) i pd pd i pu (a) (a) (a) 105 c 90 c 25 c -40 c
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 68 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller conditions: v dd = 3.3 v ; st andar d port pins. fig 32 . t y p ical pu ll-do w n cur r en t i pd ver sus in pu t vo lt a g e v i aaa-011278 0 1 2 3 4 5 0 20 40 60 80 v i (v) i pu pu i pu (a) (a) (a) -40 c 25 c 90 c 105 c
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 69 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 12. dynamic characteristics 12.1 f lash/eeprom memory [1] n umber of pro gram/er ase cycles. [2] p rogr amming times ar e given for writing 256 bytes to the flash. t am b <= + 85 ? c. flash prog ramming with iap c a lls (s ee lpc15xx user manual ). 12.2 e xternal clock fo r th e o scillator in slave mo de remark: t he inp u t vo lt age on the xt al in an d xt alout p i ns must b e ? 1.95 v (see ta b l e 1 1 ). for connecting the oscillator to the xtal pins, also see section 14.2 . [1] p aramete r s are valid over operating temp e r atur e range u nless otherw i se specified. t a ble 13. flas h ch arac teristics t amb = ? 40 ? c to + 1 05 ? c . based on jedec nvm qual ification . fa ilure rate < 10 p p m for p a rt s as specifie d belo w . symbol parameter conditions min typ max un it n en du en duran ce [1] 10 000 100 000 - cycles t re t re te nt i o n t i m e po w e red 1 0 2 0 - yea r s n o t po wered 2 0 4 0 - ye ars t er era s e time p age or multipl e co nsecutive p age s, se ctor or mu ltiple consecutive sectors 95 100 10 5 m s t pr og programming time [2 ] 0.95 1 1 .05 m s t a ble 14. eeprom characteristics t amb = ? 40 ? ct o+ 8 5 ? c; v dd = 2 .7 v t o 3 .6 v . ba sed on jedec nvm q uali f i c a t i on. f a i l ure rate < 10 pp m for p a rt s as specifie d belo w . symbol parameter conditions min typ max unit n en du endu rance 1 00 000 1 0 00 000 - cycles t re t re te ntion time p o were d 1 00 200 - y ears n o t p o wered 1 50 300 - y ears t pr og programmin g time 64 bytes - 2.9 - ms table 15. dynamic characteristic : external clock (xtalin input) t amb = ? 40 ? c to +105 ? c; v dd over specified ranges. [1] symbol parameter conditions min typ [2] max unit f os c oscill ator freq uency 1 - 2 5 m h z t cy( clk) clock cyc le tim e 40 - 1000 n s t chcx clock high time t cy (clk) ? 0. 4 - - n s t clc x clock low tim e t cy (clk) ? 0. 4 - - n s t clc h clock rise tim e - - 5 n s t chcl clock fall time - - 5 ns
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 70 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller [2] t ypical ratings are not guarante ed. the va lues list ed are for room temperatu r e (2 5 ? c) , nomin al supply vo lt ag es. 12.3 i n t ernal o scillators [1] p aramete r s are valid over operating temp e r atur e range u nless otherw i se specified. [2] t ypical ratings are not guarante ed. the va lues list ed are for room temperatu r e (2 5 ? c) , nomin al supply vo lt ag es. fig 33 . e xter nal clock timing (with a n amp l itu d e o f at least v i( rms) = 200 mv) w &+&/ w &/&; w &+&; 7 f\fon w &/&+ w &+&/ w &/&; w &+&; 7 f\fon w &/&+ w &+&/ w &/&; w &+&; 7 f\fon w &/&+ w &+&/ w &/&; w &+&; 7 f\fon w &/&+ ddd t a ble 16. dyn a mic ch ar a c teristics: ir c t amb = ? 40 ? c to + 1 05 ? c ; 2.7 v ? v dd ? 3.6 v [1 ] . symbol parameter conditions min typ [2] max unit f osc ( rc) in tern al rc oscil lator freq uen cy ? 25 ? c ? t am b ? +85 ? c 1 2 - 1% 12 12 + 1 % m h z ? 40 ? c ? t am b < ? 25 ? c 1 2 - 2% 12 12 + 1 % m h z 85 ? c < t am b ? 105 ? c 1 2 - 1.5 % 1 2 1 2 + 1.5 % m h z conditions: freq uency valu es ar e typical values. 12 mhz ? 1 % accur acy is gu aranteed for 2.7 v ? v dd ? 3.6 v and t amb = ? 25 ? c to +85 ? c. v ariations betw een p art s may cause t he ir c to fall out side the 12 mhz ? 1 % accuracy specification for volt ages below 2.7 v . fig 34 . t y p ical in tern al rc o scilla t o r freq ue nc y v e rs us temp era t ure aaa-011233 -40 -10 20 50 80 110 11.85 11.9 11.95 12 12.05 12.1 12.15 temperature (c) f osc(rc) osc(rc) f osc(rc) (mhz) (mhz) (mhz) 3.6 v 3.3 v 3.0 v 2.7 v
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 71 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller [1] t ypical ratings are not guarante ed. the va lues list ed are at nom ina l supply volt ages. [2] t he typical fr equency spr ead over pr ocessing and temper ature ( t am b = ? 40 ? c t o +1 05 ? c) is ? 40 % . 12.4 i /o pins [1] a ppli es to st andard port p i ns and reset pin. 12.5 i 2 c-bus t a ble 17. dyn a mic ch ara c terist ics: w a tch d o g os cillato r symbol parameter conditions min typ [1] max un it f os c(in t) interna l oscilla to r fre quen cy - [2] -503-khz table 18. dynamic characteristics: i/o pins [1] t amb = ? 40 ? c to + 1 05 ? c ; 3.0 v ? v dd ? 3.6 v . symbol parameter conditions min typ max unit t r rise ti me pin con f ig ured as outpu t 3 .0 - 5 .0 ns t f fall time pin configured as output 2.5 - 5.0 ns t a ble 19. dyn a mic ch ara c teristic: i 2 c-bu s pi ns [1 ] t amb = ? 40 ? c to +105 ? c; values guaranteed by design. [2] symbol parameter conditions min max un it f scl scl clock frequ ency s t and ard-mode 0 1 0 0 kh z fast-mode 0 4 00 khz fast-mode plu s ; on pins pio0_ 22 and pio0_2 3 01 m h z t f fall time [4 ] [5] [6] [7] of bo th sda an d scl signa ls standard-mode - 3 00 ns fast-mode 20 + 0.1 ? c b 30 0 n s fast-mode plu s; on pin s pio0 _22 and pio0 _23 - 1 20 ns t lo w l o w pe riod of th e sc l cl ock s t andard-mode 4.7 - ? s fast-mode 1.3 - ? s fast-mode plu s ; on pins pio0_ 22 and pio0_2 3 0.5 - ? s t hig h high peri od of th e sc l cl ock s t andard-mode 4.0 - ? s fast-mode 0.6 - ? s fast-mode plu s ; on pins pio0_ 22 and pio0_2 3 0.26 - ? s t hd;d a t dat a ho l d time [3 ] [4] [8] s t and ard-mode 0 - ? s fast-mode 0 - ? s fast-mode plu s ; on pins pio0_22 and pio0_23 0- ? s
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 72 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller [1] s ee the i 2 c-b us specification um10204 fo r det ails. [2] p aramete r s are valid over operating temp e r atur e range u nless otherw i se specified. [3] t hd;da t is the dat a hold time tha t is measured f r om the fa lling e dge of scl; a pplies to dat a in tr ansmission and the a c knowledge. [4] a device must int ernally pr ovide a hold time of at least 300 ns for the sda signal (w ith r esp ect to the v ih (min) of th e scl signal) to bridge the und efine d region of the fallin g edge of scl. [5] c b = tot al cap acit ance of one bus line in pf . [6] t he max i mum t f for t he sda and scl bu s lin es is specified a t 300 ns. the ma ximum fall time for the sda output st age t f is specified at 250 ns. this allow s se ries prote c tion resistor s to be connected in betw een the sda and the s c l pin s and the sda/scl bus lines without exceeding the maximum specified t f . [7] in fa st- m ode plu s , fall time is spe c ified the same for bo th output st age an d bus timing. if series resistor s are u s ed, d esigner s should allow for this when consider ing b us timing. [8] t he max i mum t hd ; d a t could be 3.45 ? s and 0.9 ? s for s t andar d-mode and f a st- m ode but must b e le ss than the maxi mu m of t vd ; d a t or t vd; a ck by a transition time ( s ee u m 10204 ). this ma x i mum must onl y be me t i f the device do es not str etch the low p eriod (t low ) o f the scl sign al. if t he clock stre tches the scl , the dat a must be valid b y the set- up time before it r elea s es the clo c k. [9] t su ;d a t is the dat a set-up time tha t is measured w i th r es pect t o the rising ed ge of scl; app lies to dat a in transmission and the a c knowledge. [10] a fast-mod e i 2 c - bus device can be used in a s t andard- mode i 2 c-b us system bu t the req uir ement t su ;d a t = 250 ns must then be met. this will automatically be t he case if the device d oes no t str etch the low p eriod of the scl signal. if such a device does str e tch the low per iod of the s c l signal, it must output th e next dat a bit to the sda line t r(m ax) + t su ;d a t = 1000 + 250 = 1250 n s ( accord i ng to the s t andard- mode i 2 c-bu s specification) befor e the scl lin e is released. also the acknowledge timing must meet this set-up time. t su;da t d a t a se t-up time [9 ] [10] s t and ard-mode 250 - n s fast-mode 100 - n s fast-mode plu s ; on pins pio0_ 22 and pio0_2 3 50 - ns t a ble 19. dyn a mic ch ara c teristic: i 2 c-bu s pi ns [1 ] t amb = ? 40 ? c to +105 ? c; values guaranteed by design. [2] symbol parameter conditions min max unit fig 35. i 2 c-bus pins clock timing ddd w i 6'$ w i 6 w +''$7 6&/ i 6&/ w 9''$7 w +,*+ w /2: w 68'$7
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 73 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 12.6 s pi interfaces th e maximu m dat a bit r a te is 1 7 mbi t /s in m a ste r mo de an d in slave mod e . remark: spi fu nctio n s can be assig n e d to a ll dig i t a l p i ns. the char acter i stics ar e valid fo r all dig i t a l pin s ex cep t th e op en - d r a in p i ns pio 0 _2 2 an d pio 0 _2 3. table 20. spi d yna mic c h ar acter is tics t amb = ? 40 ? c to 105 ? c ; 2. 4 v < = v dd < = 3.6 v ; c l = 10 pf ; in put sl ew = 1 ns. simul a ted p a rame ters sample d at the 50 % le vel of the risin g or fal ling e dge ; valu es g uaran te ed by desig n. symbol parameter min max unit spi maste r t ds da t a set-up time 30 - n s t dh da t a ho ld time 0 - ns t v( q) da t a ou tp ut val id time - 4 ns t h( q) da t a ou tp ut h o ld time 2 - ns spi slave t ds da t a set-up time 6 - ns t dh da t a ho ld time 0 - ns t v( q) da t a ou tp ut val id time - 2 9 n s t h( q) da t a ou tp ut h o ld time 12 - n s t cy( clk) = cc lk/divv a l with cc lk = system clo c k fr e quency . divv al is th e spi clock divider . see the lpc15 x x user manu al um1 0736 . fig 36 . spi mas ter timing 6&.&32/ 026, 0,62 7 f\fon w '6 w '+ w y4 '$ 7$9 $/,' '$ 7 $ 9 $/,' w k4 6&.&32/ '$ 7$9 $/,' '$ 7 $ 9 $/,' 026, 0,62 w '6 w '+ '$ 7 $ 9 $/,' '$ 7 $ 9 $/,' w k4 '$7$9 $/,' '$ 7 $ 9 $/,' w y4 &3+$ &3+$ ddd
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 74 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller fig 37 . spi slave timing 6&.&32/ 026, 0,62 7 f\fon w '6 w '+ w y4 '$7$9$/,' '$7$9$/,' w k4 6&.&32/ '$7$9$/,' '$7$9$/,' 026, 0,62 w '6 w '+ w y4 '$7$9$/,' '$7$9$/,' w k4 '$7$9$/,' '$7$9$/,' &3+$ &3+$ ddd
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 75 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 12.7 u sart in terface th e maximu m usar t bit ra te is 15 mb it/s in synch r on ou s mo de ma ster mod e an d 1 8 mbit/s in synchr ono us sla v e m ode . remark: usar t fu nctio n s can be assig ned to a ll di git a l pin s. t h e c h a r a ct e r i stics ar e va lid for a ll digit a l p i ns exce pt th e ope n- dr ain p i ns pio0 _22 and pio0 _23 . t a ble 21. usart d y n a mic ch arac teristics t amb = ? 40 ? c to 105 ? c ; 2. 4 v < = v dd < = 3.6 v ; c l = 10 pf ; in put sl ew = 10 ns. si mu lated p a rame ters sample d at the 50 % le vel of the fall ing or rising e dge ; valu es g uaran te ed by desig n. symbol parameter min max unit usart ma ster (in syn ch ron o u s mo de) t su(d) data input set-up time 33 - ns t h( d ) d a t a i nput hol d time 0 - ns t v( q) d a t a o u tput va lid time - 7 ns t h( q) da t a ou tp u t ho l d ti me 2 - n s usart s la v e ( in sy n c h r ono us mo de ) t su (d ) d at a i nput set-u p ti me 13 - ns t h( d ) d a t a i nput hol d time 0 - ns t v( q) da t a ou tp u t vali d ti me - 2 8 n s t h( q) da t a ou tp u t ho l d ti me 1 2 - n s in master mod e, t cy(cl k) = u_pclk/brgv a l. see the lpc15xx user manual um10736 . fig 38 . usart ti ming 8qb6&/.&/.32/ 7;' 5;' 7 f\fon w vx' w k' w y4 67$5 7 %,7 w k4 8qb6&/.&/.32/ 67 $5 7 %,7 %,7 %,7 ddd
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 76 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 12.8 s ct output timing 13. characteristics of analog peripherals [1] inter rupt levels are selected by writing the le vel value to the bod co ntrol register bodct rl, see the lpc15xx user manual . t a ble 22. sct o u tp ut dyn a mic ch ara c teristics t amb = ? 40 ? c to 105 ? c ; 2. 4 v < = v dd < = 3.6 v c l = 10 p f . simul a ted skew (over process, vol t a ge, and te mp erature) of an y two sct fi xed - pin o u tput sign als; sample d at th e 50 % leve l of th e falli ng o r rising e dge ; valu es g uaran te ed by desig n. symbol parameter conditions min typ max unit t sk(o ) output skew time sct i mer0/pwm - - 4 ns sct i mer1/pwm - - 3 ns sct i mer2/pwm - - 1 ns sctimer3/pwm - - 2 ns table 23. bod static characteristics [1] t amb =25 ? c. symbol parameter conditions min typ max unit v th thresh old volt ag e i nterrupt level 2 a sserti o n - 2.55 - v de-assertion - 2.69 - v in te rru p t l e ve l 3 a sserti o n - 2.83 - v de-assertion - 2.96 - v re se t le vel 2 a sserti o n - 2.34 - v de-assertion - 2.49 - v re se t le vel 3 a sserti o n - 2.64 - v de-assertion - 2.79 - v
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 77 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller [1] t he input r esist ance of adc chann el 0 is high er than f or all oth er channels. [2] t he dif f eren tial linear ity er ror ( e d ) is the dif fer ence between t he act ual step wid th a nd the ideal step wid th. see figur e 40 . [3] t he integr al non-line arity ( e l(a d j) ) is the peak dif fe r ence betwee n the c enter of the ste p s o f the actual and the ideal transfer curve after appropriate adj ustment of gain and offset errors. see figure 40 . [4] t he of fset er ror (e o ) is the absolute dif ference betw een the straight line which fit s the actual cur v e and the st raight line w hich fit s t he ide al curve. see f i gu re 40 . [5] the full-scale error voltage or gain error (e g ) is the difference between the straight line fitting the actual transfer curve after removing offset error, and the stra ight line which fits the ideal transfer curve. see figure 40 . [6] t am b = 25 ? c; ma ximum sampling fr equency f s = 2 msamples/s an d analog in put ca p acit ance c ia = 0.1 p f . [7] i nput impedan ce z i is inver s ely prop ortional to the samp ling fr equency and the tot al input cap acity including c ia and c io : z i ? 1 / (f s ? c i ). see table 11 for c io . t a ble 24. 12-bit adc st at ic chara c teristics t amb = ? 40 ? c to + 1 05 ? c; v dd = 2.4 v to 3.6 v ; vref p = v dd a ; v ssa = 0; vrefn = v ssa . symbol parameter co nditions min max unit v ia a nalo g inpu t vol t ag e [1 ] 0v dd a v c ia a nalo g inpu t cap a cit ance -0 . 3 2 p f f clk( adc) adc clo ck freque ncy v dd a ?? ? 2. 7 v 50 m h z v dd a ?? ? 2. 4 v 25 m h z f s sa mp ling frequ ency v dd a ?? ? 2. 7 v - 2 m sam pl e s/s v dd a ?? ? 2. 4 v - 1 m sam pl e s/s e d d if f e rential l inea rity err o r [2 ] -+ / - 2 l s b e l( adj) i n tegral no n-lin earity [3 ] -+ / - 2 l s b e o offset error [4 ] -+ / - 3 l s b v er r(fs) ful l-sca le error volt age 2 msampl es/s [5 ] - + /- 0.12 % 1 msampl es/s + / - 0.07 % z i i nput imped ance f s = 2 msample s /s [6 ] [7 ] 0. 1 - m ? fig 39 . adc input im pedance dac adc r sw = 5 ...25 r 1 = 0.25 k...2.5 k c ia c dac adcn_0 adcn_[1:11] aaa-011748 c io c io
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 78 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller (1) e xample of an actual transfer cur v e. (2) t he ide al tr ansfer curve. (3) d if ferential linear ity err or ( e d ). (4) i nteg ral non-lin earity ( e l( ad j) ). (5) c en ter of a step of the actual t r ansfer curve. fi g 40 . 1 2-b it a d c ch a r a c t er i s ti cs 002aaf436 4095 4094 4093 4092 4091 (2) (1) 4096 4090 4091 4092 4093 4094 4095 7 123456 7 6 5 4 3 2 1 0 4090 (5) (4) (3) 1 lsb (ideal) code out vrefp - v ss 4096 of fset error e o gain error e g of fset error e o v ia (lsb ideal ) 1 lsb =
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 79 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller [1] t ypical ratings are not guarante ed. the va lues list ed are at room tempe r atur e (25 ? c), nominal supply vo lt ag es. t a ble 25. dac st atic and dy namic chara c teristics v dda = 2 .4 v to 3.6 v ; t am b = ? 40 ? c to + 1 05 ? c unle s s othe rwise specifie d; c l = 100 pf ; r l =1 0 k ? .. symbol parameter conditions min ty p [1] max unit f c(d a c) dac conversi on fre que ncy - - 500 k samples/s r o ou tput resist ance - 300 ? t s sett ling time - - 2.5 ? s e d di f f ere nti al lin earity error -- + / - 0 . 4 l s b e l( ad j ) in teg r al no n-lin earity -- + / - 3 l s b e o of fset e r ro r v dda = 3.3 v - - + /-9 l sb vdda = 2.4 v - - + /-8 l sb e g ga in error - - + /- 0.1 % v o ou tpu t volt ag e output vo lt age ran ge wi th le ss than 1 l s b d e viation ; with minimum r l con nected to groun d o r po wer su ppl y -- v dda - 0.3 v fig 41 . dac test circuit dac 10 k dvm lpcxxxx r l aaa-01 1964
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 80 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller [1] m aximum an d minimum valu es ar e measured o n samp les from t he co rners of the process matr ix lot. [2] s ettling time applies to switching between comp ar ator a nd adc channels. t a ble 26. intern al volt ag e r e fere nc e st a t ic a n d d yn amic cha rac te ristic s symbol parameter conditions min typ max unit v o output voltage t amb = ? 40 ? c to +105 ? c [1] 8 7 5 - 925 mv t am b = 25 ? c 905 mv t s(p u ) powe r -u p se tt li ng ti me to 9 9 % of v o - - 125 ? s v dda = 3.3 v ; average d over process cor ners fig 42. average internal voltage reference output voltage aaa-011179 -40 -10 20 50 80 110 890 895 900 905 910 915 920 temperature (c) voltage voltage v oltage (v) (v) (v)
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 81 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller [1] a bso l ute te mperatur e accur acy . [2] t ypical values ar e de riv ed fro m nominal simula tion (v dd a = 3.3 v ; t amb = 27 ? c ; no minal process models) . maximum values are der ived fr om worst case simulation (v dda = 2.6 v ; t amb = 105 ? c ; slow pr ocess models) . [3] inter nal volt age r eference must be pow ered be fore the t emperatur e senso r can be tur ned on. [4] s ettling time applies to switching between comp ar ator a nd adc channels. [1] m easured o v er matrix samples. [2] m easured fo r samples over p r ocess corner s. t a ble 27. t e mpe ratu re sen so r s t a ti c a n d d yn amic cha rac te ristic s v dda = 2. 4 v to 3. 6 v symbol parameter conditions min typ max un it dt se n sensor te mp er at ure ac curacy t amb = ? 40 ? c to +105 ? c [1] -- 5 ? c e l linearity error t am b = ? 40 ? c to +10 5 ? c- - 5 ? c t s(p u ) po w e r-u p settling time t o 99 % o f te mp era t ure sensor ou tpu t val u e [2] [3] -8 1 1 1 0 ? s ta ble 28. t e mpe ratu re sen so r line ar-l east-sq u ar e (l l s ) fit p a rame ters v dda = 2. 4 v to 3. 6 v fi t parameter range min typ max unit ll s slope t amb = ? 40 ? c to +105 ? c [1] - - 2. 29 - m v/ ? c ll s intercept at 0 ? ct amb = ? 40 ? c to +105 ? c [1] - 5 77.3 - mv v alue at 30 ? c [2] 50 2 - 514 mv v dda = 3.3 v ; measured on matrix samples. fi g 43. lls fit of the temperature sensor output voltage aaa-011334 -40 -10 20 50 80 110 0 200 400 600 800 temperature (c) v o v o (mv) (mv) (mv) measured temperature sensor output measured temperature sensor output measured temperature sensor output lls fit lls fit lls fit
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 82 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller [1] c l = 10 pf ; result s fr om measuremen t s on silicon samples ov er pr ocess corner s and over the full temperatur e ran ge t am b = -40 ? c t o +105 ? c. [2] input hystere s is is relative to t he refer enc e inpu t chan nel a nd is sof twar e progr ammable. t a b l e 2 9 . c om p a r a tor ch ar a c t er is ti cs v dda = 3.0 v . dl y = 0x0 in the an alo g co mp arator ctrl re gister for shortest p r op ag ati on de lay settin g. see the lpc 15xx use r manu al um107 36. symbol parameter conditions min typ max unit s t atic c h ar acter is tics i dd supply current vp > vm - 4 8 - ? a vm > vp - 3 8 - ? a v ic co mmo n -mo de in put vo lt a g e 0 - v dd a v dv o o u tput vo lt age varia t i o n 0 - v dd v v of f s e t of f s et vo l t a g e v ic = 0. 1 v - + /- 3 - mv v ic = 1. 5 v - + /- 3 - mv v ic = 2. 9 v - + /- 6 - mv dy n am i c ch ar a c t er i sti cs t st ar tu p st art-up ti me n o minal p r ocess - 4.5 6 ? s t pd p r op ag ation de lay high to low ; v dda = 3.0 v ; v ic = 0 . 1 v ; 50 mv o verdrive in put [1 ] - 86 1 30 ns v ic = 0.1 v ; rail- t o-rail input [1 ] - 1 96 25 0 n s v ic = 1 . 5 v ; 50 mv o v erdrive in put [1 ] - 68 1 10 ns v ic = 1.5 v ; rail- t o-rail input [1 ] -6 4 9 0 n s v ic = 2 . 9 v ; 50 mv o v erdrive in put [1 ] - 86 1 30 ns v ic = 2.9 v ; rail- t o-rail input [1 ] -4 8 8 0 n s t pd p r op ag ation de lay l o w to high; v dd a = 3 . 0 v ; v ic = 0 . 1 v ; 50 mv o verdrive in put [1 ] - 98 1 30 ns v ic = 0.1 v; rail-to-rail input [1] -2 4 4 0 n s v ic = 1.5 v; 50 mv overdrive input [1] - 88 1 30 ns v ic = 1.5 v; rail-to-rail input [1] - 68 1 20 ns v ic = 2.9 v; 50 mv overdrive input [1] - 84 1 10 ns v ic = 2.9 v; rail-to-rail input [1] - 98 1 80 ns v hy s h yste r e s is vo lt a g e p ositive hyste r esis; v dda = 3. 0 v ; v ic = 1. 5 v ; sett ings: 5 mv [2 ] 3- 8 m v 10 m v 8 - 13 mv 15 m v 17 - 25 m v v hy s h yste r e s is vo lt a g e n egative hysteresis; v dda = 3.0 v ; v ic = 1. 5 v ; se tt in g s : 5 mv [1 ][2 ] 3- 9 m v 10 m v 8 - 18 mv 15 m v 18 - 27 m v r lad l add er re si st an ce - - 1 - m ?
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 83 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller [1] m easured o v er a polyr esistor matr ix lo t wit h a 2 khz input signal and overdr ive < 100 ? v. [2] a ll per ipher als except co mp arator , temperatu r e sensor , and irc turned of f. t a ble 30. co mp ar ator v o lt a g e lad d er d y n a mic cha rac te ristics symbol parameter conditions min typ max unit t s(p u ) p o wer-up settlin g time to 99 % o f volt ag e ladd er o u tput va lue --30 ? s t s(s w ) switching settling time to 99 % o f volt ag e ladd er o u tput va lue -- 2 0 ? s t a ble 31. co mp ar ator v o lt a g e lad d er r e fere nce s t a t ic ch ara c teristics v dd( 3v 3) = 3.3 v ; t am b = -40 ? c to + 105 ? c; external or in tern al reference . symbol parameter conditions min typ max [1] unit e v(o) output voltage error decimal code = 00 [2 ] -0 3 m v decimal code = 08 -1.5 0 + 1.5 % decimal cod e = 16 -1.5 0 + 1.5 % decimal cod e = 24 -1.5 0 + 1.5 % decimal cod e = 30 -1.5 0 + 1.5 % decimal cod e = 31 -1.5 0 + 1.5 %
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 84 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 14. application information 14.1 s ugg ested usb in terface solu tions the usb device can be connected to the usb as self-powered device (see figure 44 ) or bus-powered device (see figure 45 ). on the lpc15xx, the pio0_3/usb_vbus p i n is 5 v tole ra nt o n ly wh en v dd is ap plie d and a t op er ating volt a ge leve l. th ere f ore , if th e usb_ vbus fu nction is co nne cted to the usb co nn e c to r an d th e de vice is se lf- p o w e r e d , the usb_vbus pin m u st b e pr otecte d for situations when v dd = 0 v . if v dd is always gre a ter th an 0 v wh ile vbus = 5 v , the usb_vbus p i n can be co nne cted d i rectly to the vbus p i n on the usb co nne cto r . fo r systems wher e v dd ca n be 0 v an d vbus is d i re ct ly a p p lie d t o th e vbus pin , pr e c au tio n s m u st be t a ke n to re du ce t h e vo lt a g e to b e l ow 3. 6 v , wh ich is th e ma xim u m a llowable vo lt age o n the usb_vbus pin in th is case. one me th od is to u s e a vo lt age d i vi der to con nect th e usb_ vbus pin to th e vbus on th e usb connec tor . the volt age divider ratio shou ld be such that the usb_vbu s pin w ill be g r ea ter tha n 0.7v dd to indicate a logic high while be low th e 3. 6 v a llow a b l e ma xim u m volt a ge. fo r the follo win g opera t ing cond itions vbus max = 5.25 v v dd = 3.6 v , th e vo lt ag e div i de r sh ou ld pr ov ide a r e d u c tio n of 3. 6 v/5 .2 5 v o r ~ 0 . 6 8 6 v . fo r a bu s-po were d de vice, the vbus sign al doe s n o t n eed to b e co nn ecte d to th e usb_vbus pin (see f i gur e 45 ). the usb_connect function can additionally be enabled internally by setting the dcon bit in the devcmdstat register to prevent the usb from timing out when there is a significant delay between power-up and handling usb traffic. external circuitry is not required for the usb_connect functionality. fig 4 4 . u sb inter f ace o n a self-po w er ed d evice whe r e usb_vbus = 5 v lpc1xxx v dd r1 1.5 k aaa-010820 usb-b connector usb_dp usb_dm usb_vbus v ss r s = 33 r s = 33 usb usb_connect r2 r3
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 85 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller remark: wh en a bu s- po we re d c i rcu i t as s h o w n in figur e 4 5 is use d o r , fo r a s e lf -p ow er ed d e vice , whe n th e vbus pin is no t conn ect ed, co nfigu r e the pio0 _3/usb_vbus p i n fo r gp io (pi o 0_3) in the io con bloc k. this t ies the vbus signal hi gh internally . 14.1 .1 u sb low-s peed o peration th e usb de vi ce con t r o lle r can b e used in lo w- spee d mod e supp or tin g 1.5 mb it/s d a t a ex ch an g e w i th a usb ho st co nt ro ller . remark: t o o per ate in low- sp ee d mod e , cha n g e th e bo ard co nne ctio ns a s follo ws: 1 . con nect usb_dp to th e d- pin of th e conn ector . 2 . con nect usb_dm to th e d+ pin of the co nne ctor . exte rn al 10 ? r e sisto r s ar e re co mme nde d in low-sp eed m ode to r e d u ce over -sho ot s a n d a c com m od ate fo r 5 m cable leng th r e q u ir ed for usb-if testing. 14.2 x t a l inpu t and cryst al osci llator component selection the input voltage to the on-chip oscillators is limited to 1.8 v. if the oscillator is driven by a clock in slave mode, it is recommended that th e input be coupled through a capacitor with c i = 100 pf. to limit the input voltage to the specified range, choose an additional capacitor to ground c g which attenuates the input voltage by a factor c i /(c i + c g ). in slave mode, a minimum of 200 mv(rms) is needed. f i g 4 5 . usb inter f ace o n a bu s-po we red d e v i ce regulator vbus lpc1xxx v dd r1 1.5 k aaa-010821 usb-b connector usb_dp usb_dm v ss r s = 33 r s = 33 usb usb_connect
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 86 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller in slave mo de the i npu t clock sig nal sho u ld b e coup led b y me an s of a cap a citor o f 1 0 0 p f ( figu re 4 6 ) , with a n am plitude b e tween 2 0 0 m v ( r m s ) and 100 0 m v (rms). this cor r e s p o n d s to a squ a r e wa ve sig nal with a sig n a l swing of be twee n 28 0 mv and 1 . 4 v . th e xt al out pin in this co nfigu r atio n ca n be le f t un conn ecte d. external components and models used in oscillation mode are shown in figure 47 and in ta b l e 3 2 and ta b l e 3 3 . since the feedback resistance is integrated on chip, only a crystal and the capacitances c x1 and c x2 need to be connected externally in case of fundamental mode oscillation (the fundamental frequenc y is represen ted by l, c l and r s ). capacitance c p in figure 47 represents the parallel package capacitance and should not be larger than 7 pf. parameters f osc , c l , r s and c p are supplied by the crystal manufacturer (see ta b l e 3 2 ). fig 46 . s la ve mo de o p er ation o f th e on -chip o scillato r fig 47 . o s c illato r mod es an d mo dels: os cillation m o d e of op era t io n an d exter na l cry s t a l mo del use d for c x1 /c x2 eva luation t a ble 32. rec o mme nd ed v alu es fo r c x1 /c x2 in os cillation m o d e (c rys t a l an d exte rna l compone n t s p a r a me te rs) low fre q uenc y mode f u n d a men t a l os cillation frequency f osc crys t a l load cap acit a nc e c l ma xim u m cr yst al s e ries re sist anc e r s exter n al lo ad cap acitor s c x1 , c x2 1 m hz to 5 m hz 10 pf < 300 ? 18 pf , 18 pf 20 pf < 300 ? 39 pf , 39 pf 30 pf < 300 ? 57 pf , 57 pf lpc1xxx xt alin c i 100 pf c g 002aae788 002aaf424 lpc1xxx xtalin xtalout c x2 c x1 xt al = c l c p r s l
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 87 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 14.3 x t a l printed-circuit boar d (pcb) layout guidelines the crys t a l s h ould be connected on the pc b as c los e as poss ible to the oscillator input a nd outpu t pin s of the chip. t a ke care tha t th e lo ad cap a citors c x1 , c x2 , a nd c x3 i n ca se o f thir d over tone cr yst a l u s a ge ha ve a co mmo n gr oun d pla ne. the e x te rna l co mpo nen t s mu st also b e co nne cted to th e g r o und p l ane . lo op s must be ma de as sma ll as p o ssible in or d e r to ke e p th e no ise co up le d in via th e pcb a s sm all as po ss ible . a l so p a ra sitic s sh ou ld st a y a s sm all as po ss ible. s m aller v a lues of c x1 a nd c x2 sh ou ld be cho s e n ac cording t o the increase in p a rasit ics of the pcb layout. 5 m hz to 10 mhz 10 pf < 300 ? 18 pf , 18 pf 20 pf < 200 ? 39 pf , 39 pf 30 pf < 100 ? 57 pf , 57 pf 10 mhz to 1 5 mh z 10 pf < 160 ? 18 pf , 18 pf 20 pf < 60 ? 39 pf , 39 pf 15 mhz to 2 0 mh z 10 pf < 80 ? 18 pf , 18 pf t a ble 33. rec o mme nd ed v alu es fo r c x1 /c x2 in os cillation m o d e (c rys t a l an d exte rna l compone n t s p a r a me te rs) hi gh freq uen cy mo de fundamental oscillation frequency f osc crystal load capacitance c l maximum crystal series resistance r s exter n al lo ad cap acitor s c x1 , c x2 15 mhz to 2 0 mh z 10 pf < 180 ? 18 pf , 18 pf 20 pf < 100 ? 39 pf , 39 pf 20 mhz to 2 5 mh z 10 pf < 160 ? 18 pf , 18 pf 20 pf < 80 ? 39 pf, 39 pf t a ble 32. rec o mme nd ed v alu es fo r c x1 /c x2 in os cillation m o d e (c rys t a l an d exte rna l compone n t s p a r a me te rs) low fre q uenc y mode fundamental oscillation frequency f osc crystal load capacitance c l maximum crystal series resistance r s external load capacitors c x1 , c x2
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 88 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 14.4 r tc oscillator component selection the 32 khz crystal must be connected to the part via the rtcxin and rtcxout pins as shown in figure 48 . if the r t c is not us ed, t h e r t c x in pin can be grounded. select c x1 an d c x2 ba se d on the e x te rna l 32 khz cryst a l used in the a ppl ica t io n circui tr y . t he p ad cap a cit a n c e c p o f the r t cxin and r t cxout p ad is 3 p f . if th e exte rn al cryst al? s load ca p a cit a nce is c l , th e op tim a l c x1 and c x2 can be se lecte d as: c x1 = c x2 = 2 x c l ? c p fig 48 . rt c o scilla t or co mp on ent s lpc1xxx rtcxin rtcxout c x2 c x1 xt al = c l c p r s l aaa-010822
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 89 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 15. package outline f i g 4 9. p ac kag e ou tline l q f p 48 (sot 313 -2) unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v references outline version european projection issue date iec jedec jeita mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 7.1 6.9 0.5 9.15 8.85 0.95 0.55 7 0 o o 0.12 0.1 0.2 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot313-2 ms-026 136e05 00-01-19 03-02-25 d (1) (1) (1) 7.1 6.9 h d 9.15 8.85 e z 0.95 0.55 d b p e e b 12 d h b p e h v m b d z d a z e e v m a 1 48 37 36 25 24 13 a 1 a l p detail x l (a ) 3 a 2 x y c w m w m 0 2.5 5 mm scale pin 1 index lqfp48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm sot313-2
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 90 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller f i g 5 0. p ac kag e ou tline l q f p 64 (sot 314 -2) unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v references outline version european projection issue date iec jedec jeita mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 10.1 9.9 0.5 12.15 11.85 1.45 1.05 7 0 o o 0.12 0.1 1 0.2 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot314-2 ms-026 136e10 00-01-19 03-02-25 d (1) (1) (1) 10.1 9.9 h d 12.15 11.85 e z 1.45 1.05 d b p e e a 1 a l p detail x l (a ) 3 b 16 c d h b p e h a 2 v m b d z d a z e e v m a x 1 64 49 48 33 32 17 y pin 1 index w m w m 0 2.5 5 mm scale lqfp64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm sot314-2
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 91 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller f i g 5 1 . p ac kag e ou tline l q f p 100 (sot40 7-1) unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v references outline version european projection issue date iec jedec jeita mm 1.6 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 14.1 13.9 0.5 16.25 15.75 1.15 0.85 7 0 o o 0.08 0.08 0.2 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot407-1 136e20 ms-026 00-02-01 03-02-20 d (1) (1) (1) 14.1 13.9 h d 16.25 15.75 e z 1.15 0.85 d b p e e a 1 a l p detail x l (a ) 3 b 25 c d h b p e h a 2 v m b d z d a z e e v m a x 1 100 76 75 51 50 26 y pin 1 index w m w m 0 5 10 mm scale lqfp100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm sot407-1
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 92 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 16. soldering f i g 5 2. re f lo w so ld erin g for the l q f p 48 p a cka ge sot313-2 dimensions in mm occupied area footprint information for reflow soldering of lqfp48 package ax bx gx gy hy hx ay by p1 d2 (8 ) d1 (0.125) ax ay bx by d1 d2 gx gy hx hy 10.350 p2 0.560 10.350 7.350 7.350 p1 0.500 0.280 c 1.500 0.500 7.500 7.500 10.650 10.650 sot313-2_fr solder land c generic footprint pattern refer to the package outline drawing for actual layout p2
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 93 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller f i g 5 3. re f lo w so ld erin g for the l q f p 64 p a cka ge sot314-2 dimensions in mm occupied area footprint information for reflow soldering of lqfp64 package ax bx gx gy hy hx ay by p1 p2 d2 (8 ) d1 (0.125) ax ay bx by d1 d2 gx gy hx hy 13.300 13.300 10.300 10.300 p1 0.500 p2 0.560 0.280 c 1.500 0.400 10.500 10.500 13.550 13.550 sot314-2_fr solder land c generic footprint pattern refer to the package outline drawing for actual layout
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 94 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller f i g 5 4. re f lo w so ld erin g for the l q f p 100 p ack age sot407-1 dimensions in mm occupied area footprint information for reflow soldering of lqfp100 package ax bx gx gy hy hx ay by p1 p2 d2 (8 ) d1 (0.125) ax ay bx by d1 d2 gx gy hx hy p1 p2 c sot407-1 solder land c generic footprint pattern refer to the package outline drawing for actual layout 17.300 17.300 14.300 14.300 0.500 0.560 0.280 1.500 0.400 14.500 14.500 17.550 17.550
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 95 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 17. references [1] lpc15xx user manual um10736: http://www.nxp.com/documen ts/user_manual/um10736.pdf [2] lpc15xx errata sheet: http://www.nxp.com/documents /errata_sheet/es_lpc15xx.pdf 18. revision history t a b le 3 4 . r ev is i on hi st ory document id release date data sheet status change notice su pe rsed es lpc15xx v.1 20140219 product data sheet - -
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 96 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 19. legal information 19.1 dat a sheet st atus [1 ] p le ase con s ul t t h e mo st r e cent ly iss ued do cum e n t b e fo r e i n i t i a ti ng or co mp l e ti ng a de sig n . [2 ] t h e te r m ? sh o r t d a t a sh ee t? is e xplaine d i n secti o n ?de finition s?. [3 ] t h e pr od uct st a tus o f de vice ( s ) d e scr i bed i n th is d o cu me nt m a y h a ve cha nge d si nce thi s d o cum e nt w a s p u b l i s h e d a n d ma y di f fe r in case of mu ltip le de vice s . the la test p r o d u c t st atu s i nf or m ati on i s a v ai l abl e on th e i ntern et at u r l htt p :// w w w .nxp .com . 19.2 definitions dr a f t ? the do c u m e nt is a draf t versi on onl y . the cont ent is st ill unde r int e rn al review and subje c t to f o rmal ap proval, which m a y re su lt in modif i cat i ons or add itio ns. nxp se miconduct o rs does not g i ve a n y rep resent a t io ns o r wa rrant ies as t o t he accu racy or compl e te ness o f inf o rma tio n in c l u ded her ein and shall hav e no liab ilit y fo r t he consequ ences o f use of such inf o rmat i on . short dat a sheet ? a shor t dat a she et is an extr act fr om a f ull da t a sh eet wit h t he same pr oduct t y pe numbe r(s) and t i t l e. a shor t dat a sh eet is int end ed for qu ick r efe rence only an d shou ld no t b e rel i ed u pon to cont ain det ailed and fu ll inf ormat i on. for det a iled and f ull inf orma tio n se e t he re levant f ull da t a sheet , which is availab l e on requ est vi a the lo c a l nx p semicond ucto rs sale s of fi ce . in case of a ny in co nsist en c y or conf lict wit h t he shor t dat a she et, th e fu ll dat a shee t shall pre v a il. p r o d u ct sp ec if i c a t io n ? the inf orma tio n and dat a p r ovide d i n a p r oduct dat a she et shal l d efi ne the spe c if icat ion of the pr oduct a s agr eed be tween nxp se mico nduct ors and it s cu st omer , u n less nx p s e micond uctor s an d custome r have explicit ly ag reed ot her wis e i n wri t in g. i n no event h owever , shall an ag reemen t be valid in which t he nxp semi co nduct ors p r odu ct is dee med to of f er fu nctio ns and quali t ies beyon d t hos e descri bed in th e pro duct da t a sh eet . 19.3 disclaimers li mi te d wa rr a n ty an d li a b il it y ? i nf ormat i on in th is documen t is bel ieved to be accurat e and re liabl e. however , nxp s emicondu ct ors doe s not give any rep resent a t io ns o r wa rrant ies, e x p ressed or implie d, as to t he accuracy or completen e ss of such informa tio n a nd shall have no lia bility for the consequ ences o f use of such inf o rmat i on . nxp se mico nduct ors t akes no respo n sibilit y f o r t he c o nt ent in t h is documen t if pr ovided by an inf o rmat i on source out si de of nxp s emicondu ct ors. in n o e v e nt shall nxp s emicond uctor s be lia ble fo r a ny in dire ct , in cid ent a l , pun itive, spe c i a l or consequ ent ial damag es (inclu ding - wit hou t limit a t io n - lost prof it s , lost savings, business int e rrupt ion, cost s related t o the remov a l or rep l acement of an y pro duct s o r rework ch arge s) whe t he r or not such dama ges a r e based on t ort ( i ncludi ng negli gence) , warra nty , bre ach of cont ract or an y ot her le gal th eory . not with s t andin g a n y d a mages th at cust omer might incur fo r any r eason what soe v e r , nxp semi co nduct ors? ag greg at e and cumulat i ve l i abil i ty t oward s custome r for t he pro duct s d escr i bed he rein shall be li mite d i n a c cor dance wit h t he t e rms a nd condit i on s of comme rcial sale of nxp s e micondu ct or s. ri ght to m ake c h a n ge s ? nx p semicon ducto rs re s e rves t he rig ht t o ma k e chang es t o inf o rmat i on pu blished in t his documen t, i ncludin g wit ho ut limit a t io n sp ecificat ion s an d p r odu ct descript i ons, a t any time a nd with out not ice. this documen t super sed e s a nd repla c e s all inf o rma tio n sup p lied pr ior to t he pu blicat ion her eof . s u i t a b il it y f o r us e ? nxp s e micond uctor s pro ducts are not designe d, aut hori z e d o r w a rran t ed t o be suit ab le fo r u s e in li fe suppo rt , lif e-crit ical or sa fe ty-crit i cal syst ems or e quipme n t, nor in app licat ions where f a ilur e or malf unct i on of an nx p s emicond uctor s pro duct can rea s o nabl y be expe ct ed to result in per sonal inju ry , d eat h or seve re prop ert y or envi ronme nt al damag e. nxp s e micondu c t ors and it s suppl iers a c cep t no lia bilit y f o r inclusion an d/ or use o f nxp se mico nduct o rs prod uct s in such equ ipment or appl ica t io ns and t her efo r e such inclu s io n and /or use is at t he cu st omer ? s own risk. ap plic ation s ? a ppli c a t ions t hat a r e describe d h erei n f or an y of t hese prod uct s ar e for il lustra tive pu rpos es only . nxp se mico nduct o rs makes no repr esent a t io n o r wa rran t y tha t such a pplication s will be suit a b le for the specifi ed use w i tho ut f urt her t esti ng or modif i cat i on. custome rs ar e responsib le for t he desig n a nd ope rat i on of t hei r a pplicat ion s and pr oduct s using nxp s emicondu ct or s pro duct s, and nxp semi conduct ors acce pt s no liabi lity fo r any a s sist a n ce wit h app licati ons o r cu st omer pr oduct design . it is cust omer ? s sol e r e sponsib ilit y t o d e t e rmine whe t he r t h e nxp semicon ducto rs p r odu ct is sui t able a nd f i t f or t he custome r ? s a pplicat ion s an d prod uct s pl anne d, as well as f o r t he plan ned app licati on and use of cu st ome r ? s t h ird p a rt y cust omer( s ) . custo mers sho u ld pro v id e appro p ria t e design an d o pera t in g saf eg uard s t o min i mize the r i sks asso cia t e d wit h t heir appl ica t ions a nd prod uct s. nxp semicon duct o rs d oes n o t accept any liabil i ty rela ted t o any def ault , damag e, cost s o r probl em wh ich is based on a n y weakne ss or def aul t in th e cu st ome r ? s ap plicat ions or prod uct s , or t he appl ica t io n o r use b y custo m er ? s th ird p a rt y custo mer(s). c u st omer is respo n sible f o r doing a ll n e cessa ry te st ing f o r th e cu st omer ? s app lic at ions and pro duct s u s i ng nxp semicon ducto rs p r oduct s in orde r to av oid a de fau l t of the ap plicat ions and th e p r odu ct s or of t he ap plicat ion or use by cu st omer ? s t hird p art y cu st ome r(s). nxp d oes n ot accept a n y liab ilit y in t h is r e sp ec t. li mi ting v a l ues ? s t ress above one or mo re limit ing values (as def ined in th e a b solut e maximum rati ngs s y s t em of i e c 6013 4) will c a use p e rman ent damag e t o the device. li miti ng va lues are stre ss rat i ngs onl y and (prope r) oper ati on of t he device at t hese or an y ot her cond iti ons a bove th ose g i ven in th e re co mm e nded o perat ing con dit ions se ct ion (if presen t) or t he chara c t e rist ics sect ions of t h is d o cument is no t warra nte d . const a nt or repe ate d exposure t o limit ing values will perma nent ly and irre v e rsibly af f e ct th e q uality a nd relia bility o f th e device. t e rms a n d condi tions o f comm ercial s a le ? n x p semic onduc tors prod uct s ar e so ld su bject t o the g ener a l t er m s and cond iti ons o f commercial sa le, a s pub lished at ht tp :/ /www .n xp .c om / p ro file /t er m s , unle s s ot herwise agre ed in a va lid writ ten in dividua l a gree m ent . in case an ind i vidual agre ement is conclud ed only th e t er m s and cond iti ons o f t he respect i ve agre ement sh all appl y . nxp s emicondu ct ors her eby e x p r essly ob ject s t o appl yin g the cust omer ? s gene ral te rms an d con dit ions with re gard t o th e purcha s e of nxp semicon duct o rs p r odu ct s by cu st omer . no offe r to sel l or l i ce nse ? not h ing i n th is documen t may be int e rpr e t ed or co nstr ued a s an of f er t o sel l pro duct s t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. document status [1] [2] product status [3] defi niti on obje ct ive [sho rt] dat a shee t d evelop ment this d ocument con t ain s dat a fro m t he obj ecti ve specif icati on fo r p roduct d e velop ment . preli minary [sho rt] dat a shee t q ua lif ica t io n t his d o cument con t ain s dat a fro m t he pre liminar y specif icat ion. product [short] data sheet production this document contains the product specification.
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 97 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller export con t r ol ? t h is do cu ment a s well as the it em(s) de scrib ed here i n may b e su bject t o export co ntr ol regu lat i ons. expo rt migh t req uire a pri or aut hor izati on fro m compe t e nt au tho r it ies. non - autom o tive qual i fied p r oduct s ? unl e ss t h is d a t a sheet expressly st at es th at thi s spe c i f ic nxp semicon duct ors prod uct i s a uto mot i ve qual ifi ed, th e p roduct is n o t suit a b le for aut omo t ive use. it i s neit her qua lif ied nor test ed in accorda n ce wit h aut omot ive te st ing o r a pplicat ion re quire ment s. nx p semi co nduct o rs a c cep t s n o l i abili ty for in cl usion and/ or use of non -aut omot ive qual ifie d produ ct s in au tomo tive equ ipmen t or app licati ons. in t he even t th at custo m er uses t he pro duct f o r desig n-in and u s e in aut omot ive app licat ions t o aut omot ive s pecif ica t io ns and st an dard s , custome r (a) shal l u s e t he pro duct wit hout n x p semicon ducto rs? wa rrant y o f t he pro duct f o r su ch a u to moti ve ap plicat ions, u s e a nd sp ecifi c a t io ns, and (b ) whene ve r cust omer uses the p r odu ct for au to m o tive ap plicat ions beyond nxp semicon ductors? s p ecification s such use sh all be so lely at custo m er ? s own risk, and (c) custo mer ful l y ind e mnif ies nxp semicon duct o rs f o r an y liabi lity , da mages or f ailed p r odu ct cl aims r esult ing f r om custome r design an d use of t he prod uct f or aut omot ive a pp licat ion s be yo nd nxp semicon duct o rs? st anda rd warra nty and nxp s emicondu ct ors? pro duct specif icat ions. 19.4 t r ademarks noti ce : all r efe renced b r ands, prod uc t name s , service names and t rad emarks are t he prop ert y of the i r respect i ve o w ners. i 2 c-bus ? logo is a trademark of nxp b.v. 20. cont act information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
lp c15x x a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 4 . al l r i ght s r e se r v ed. product data sheet rev. 1 ? 19 february 2014 98 of 99 continued >> nxp semiconductors lpc15xx 3 2 - bit arm cort ex -m3 micr ocon tro l ler 21. content s 1 g e n e ral descrip t io n . . . . . . . . . . . . . . . . . . . . . . 1 2 f e atu r es and b e n e fit s . . . . . . . . . . . . . . . . . . . . 1 3 app li c ati o n s . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 o r d e ri ng in formatio n . . . . . . . . . . . . . . . . . . . . . 4 4.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 5 5 marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 blo c k diag ram . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7 pi nn ing i n fo rmatio n . . . . . . . . . . . . . . . . . . . . . . 8 7.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . 12 8 f u n c ti on al d e scri p ti on . . . . . . . . . . . . . . . . . . 21 8.1 arm cortex-m 3 processor . . . . . . . . . . . . . . . 21 8.2 memory prot ect i on unit (m pu) . . . . . . . . . . . . 21 8.3 on-chip flash pr ogramming memory . . . . . . . 22 8.3.1 isp pin configuration . . . . . . . . . . . . . . . . . . . 22 8.4 eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.5 sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.6 on-chip rom . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.7 ahb multilay e r matrix . . . . . . . . . . . . . . . . . . . 24 8.8 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.9 ne sted v e ctored interrupt controll er (nvic) . . 26 8.9.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.9.2 interrupt sources . . . . . . . . . . . . . . . . . . . . . . . 26 8.10 io co n block . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.10. 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.10. 2 s t andard i/o p a d conf iguration . . . . . . . . . . . . 26 8.1 1 swit ch matrix (swm ) . . . . . . . . . . . . . . . . . . . 27 8.12 fast gener a l-purpos e p a rallel i /o (gpi o) . . . 28 8.12. 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.13 pin i n te rrupt/p attern match eng ine (pint) . . . 2 8 8.13. 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.14 gpio g r oup in te rru p t s (gint 0 /1) . . . . . . . . . . 2 9 8.14. 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.15 dma controller . . . . . . . . . . . . . . . . . . . . . . . . 29 8.15. 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.16 input multiplexing (input mux) . . . . . . . . . . . . 30 8.17 usb interface . . . . . . . . . . . . . . . . . . . . . . . . 30 8.17 .1 f u ll -sp eed usb device con t ro ller . . . . . . . . . . 3 0 8.17. 1 . 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.18 usar t 0 /1/2 . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.18. 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.19 spi0/1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.19. 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.20 i2c-bus int e rf ac e . . . . . . . . . . . . . . . . . . . . . . 32 8.20. 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.21 c_can . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8. 21. 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8. 22 pwm /ti me r/m o t o r co nt ro l subsys tem . . . . . . . 33 8.22.1 sctimer/pwm s ubsystem . . . . . . . . . . . . . . . 33 8. 22 . 2 t i m e r co nt ro ll e d su bsy ste m . . . . . . . . . . . . . . 34 8 . 2 2.3 sct i me r/pw m in the la rg e configu r a t i on (sct0/1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8. 22. 3 . 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8 . 2 2 .4 s t ate-config urabl e t imers i n the smal l conf iguration ( sct 2/3) . . . . . . . . . . . . . . . . . . 37 8. 22. 4 . 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8. 22. 5 sct i n put processing unit (sctip u) . . . . . . . 38 8. 22. 5 . 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8. 23 quadrature encoder inte rface (q ei) . . . . . . . 39 8. 23. 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8. 24 analog-t o-digit a l convert e r (adc) . . . . . . . . . 39 8. 24. 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8. 25 digit a l-to-analog convert e r (dac) . . . . . . . . . 40 8. 25. 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8. 26 analog comp arator (acmp) . . . . . . . . . . . . . . 40 8. 26. 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8. 27 t e m p erature sensor . . . . . . . . . . . . . . . . . . . . 41 8 . 2 8 interna l vo lt age referen c e . . . . . . . . . . . . . . . 41 8. 29 mult i- rate t i m e r (mr t) . . . . . . . . . . . . . . . . . 42 8. 29. 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8 . 3 0 w ind owed w a tchdo g t i mer (ww d t) . . . . . . 42 8. 30. 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8. 31 repetitive interrupt (ri) t i m e r . . . . . . . . . . . . . 43 8. 31. 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8. 32 system tick t i m e r . . . . . . . . . . . . . . . . . . . . . . 43 8. 33 real-t ime clock (r t c ) . . . . . . . . . . . . . . . . . 43 8. 33. 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8. 34 clock generat i on . . . . . . . . . . . . . . . . . . . . . . 44 8. 35 power domains . . . . . . . . . . . . . . . . . . . . . . . 45 8 . 3 6 integra t e d oscilla to rs . . . . . . . . . . . . . . . . . . . 45 8 . 3 6 .1 interna l rc oscilla to r . . . . . . . . . . . . . . . . . . . 46 8. 36. 2 system osc i llato r . . . . . . . . . . . . . . . . . . . . . . 46 8. 36. 3 w a tchdog oscillator . . . . . . . . . . . . . . . . . . . . 46 8. 36. 4 r t c oscillator . . . . . . . . . . . . . . . . . . . . . . . . 46 8 . 3 7 system pl l, usb pll, and sct pl l . . . . . . 46 8. 38 clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 47 8. 39 w a ke-up process . . . . . . . . . . . . . . . . . . . . . . 47 8. 40 power c o ntrol . . . . . . . . . . . . . . . . . . . . . . . . . 47 8. 40. 1 power profiles . . . . . . . . . . . . . . . . . . . . . . . . 47 8 . 4 0 .2 sl eep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 47 8. 40. 3 deep-sleep mode . . . . . . . . . . . . . . . . . . . . . . 48 8. 40. 4 power-down mode . . . . . . . . . . . . . . . . . . . . . 48 8. 40. 5 deep power-down mode . . . . . . . . . . . . . . . . 48 8. 41 system contro l . . . . . . . . . . . . . . . . . . . . . . . . 49
nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller ? nxp b . v . 20 14. al l r i g h t s re se rv ed. for m o r e i n for m a t i o n , plea se visit: htt p :// w ww.n x p.co m for sale s of fice a d d r e sses, plea se se nd an ema i l t o : s a lesa ddre sses@ nxp . com date of release: 19 february 2014 document identifier: lpc15xx please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 8.41. 1 res e t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 8.41. 2 brownout detection . . . . . . . . . . . . . . . . . . . . . 49 8.41 .3 co de security (c ode rea d pro t e c ti on - cr p) 4 9 8.42 emula t i on and d ebug gin g . . . . . . . . . . . . . . . . 5 1 9 l i miti ng val u es . . . . . . . . . . . . . . . . . . . . . . . . . 51 10 t h ermal characteri s tics . . . . . . . . . . . . . . . . . 52 1 1 s t atic ch aract e risti c s . . . . . . . . . . . . . . . . . . . . 54 1 1 . 1 power consumption . . . . . . . . . . . . . . . . . . . . 59 1 1 . 2 cor e mark dat a . . . . . . . . . . . . . . . . . . . . . . . . 63 1 1 . 3 pe ri ph e r al po w e r co n s um pt ion . . . . . . . . . . . . 64 1 1 . 4 elect rical pin characteristics . . . . . . . . . . . . . . 65 12 dynamic characteristics . . . . . . . . . . . . . . . . . 69 12.1 flash/eeprom memory . . . . . . . . . . . . . . . . 69 12 .2 external clo c k for th e o scilla to r in sla v e mo de 6 9 12. 3 internal osc i llators . . . . . . . . . . . . . . . . . . . . . . 70 12. 4 i/ o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 12 .5 i 2 c-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 12. 6 spi int e rf ac es . . . . . . . . . . . . . . . . . . . . . . . . . 73 12. 7 usar t interface . . . . . . . . . . . . . . . . . . . . . . . 75 12. 8 sct output timing . . . . . . . . . . . . . . . . . . . . . . 76 13 cha rac te ristics of an alog perip h eral s . . . . . . 76 14 ap pli c ati o n in formatio n . . . . . . . . . . . . . . . . . . 84 14 .1 sug gested usb interface solutions . . . . . . . . 84 14 .1 .1 usb low-sp eed op eration . . . . . . . . . . . . . . . 8 5 14 .2 xt al i nput and cryst a l oscilla to r compo nen t select ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 14 .3 xt al prin te d-circui t board (pcb) l a you t guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 14 .4 r t c oscil lator co mp one nt sel e cti o n . . . . . . . . 8 8 15 packag e ou tlin e . . . . . . . . . . . . . . . . . . . . . . . . 89 16 so ld erin g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 17 referen c es . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 18 revi sion h istory . . . . . . . . . . . . . . . . . . . . . . . . 95 19 l e g a l in fo rmatio n . . . . . . . . . . . . . . . . . . . . . . . 96 19. 1 dat a sheet st at us . . . . . . . . . . . . . . . . . . . . . . 96 19. 2 def i nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 19. 3 dis c laimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 19. 4 t r ademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 20 co nt act i n fo rmatio n . . . . . . . . . . . . . . . . . . . . . 97 21 co ntent s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

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